0 00:00:00,000 --> 00:00:30,000 Dear viewer, these subtitles were generated by a machine via the service Trint and therefore are (very) buggy. If you are capable, please help us to create good quality subtitles: https://c3subtitles.de/talk/475 Thanks! 1 00:00:09,420 --> 00:00:11,669 So it's my very great 2 00:00:11,670 --> 00:00:13,949 pleasure to introduce to you, Clifford, 3 00:00:13,950 --> 00:00:16,229 who's going to talk about 4 00:00:16,230 --> 00:00:18,509 a very complex topic I know very 5 00:00:18,510 --> 00:00:20,429 little about, but that's probably going 6 00:00:20,430 --> 00:00:21,619 to change now. 7 00:00:21,620 --> 00:00:23,339 And so please give a warm round of 8 00:00:23,340 --> 00:00:25,409 applause for free and open source. 9 00:00:25,410 --> 00:00:27,629 Very luck to bitstream flow for 40 10 00:00:27,630 --> 00:00:28,630 FPGA. 11 00:00:35,340 --> 00:00:36,340 Thank you, 12 00:00:37,410 --> 00:00:39,089 so I'm talking about the free and open 13 00:00:39,090 --> 00:00:41,509 source, I look kids as far as 45 14 00:00:41,510 --> 00:00:43,739 pages and in particular, 15 00:00:43,740 --> 00:00:45,359 that means I'm going to talk about three 16 00:00:45,360 --> 00:00:47,429 projects because these 17 00:00:47,430 --> 00:00:49,499 three projects together form 18 00:00:49,500 --> 00:00:51,599 this free and open source where 19 00:00:51,600 --> 00:00:53,699 I look to bitstream floor for 20 00:00:53,700 --> 00:00:54,929 this kind of pages. 21 00:00:56,210 --> 00:00:58,619 And the project I'm going to talk about 22 00:00:59,730 --> 00:01:01,859 Project István and project 23 00:01:01,860 --> 00:01:04,259 based is an effort to 24 00:01:04,260 --> 00:01:06,419 reverse engineer and document 25 00:01:06,420 --> 00:01:08,909 the bitstream format for 40 26 00:01:08,910 --> 00:01:10,049 FPGA. 27 00:01:10,050 --> 00:01:12,269 And in particular right 28 00:01:12,270 --> 00:01:14,579 now we support the H, x1, K 29 00:01:14,580 --> 00:01:17,129 and Ajax 8-K. 30 00:01:17,130 --> 00:01:19,409 FPGA is in 31 00:01:19,410 --> 00:01:21,599 theory, we should only also support the 32 00:01:21,600 --> 00:01:24,299 LP one K and LP 33 00:01:24,300 --> 00:01:26,489 8-K if there is such 34 00:01:26,490 --> 00:01:28,889 a one. I don't know FJC 35 00:01:28,890 --> 00:01:31,049 because they just have different 36 00:01:31,050 --> 00:01:33,089 timings, but the piston format is 37 00:01:33,090 --> 00:01:34,140 absolutely identical. 38 00:01:36,630 --> 00:01:38,999 So from the Ice Storm project 39 00:01:39,000 --> 00:01:41,069 we get the documentation 40 00:01:41,070 --> 00:01:43,169 for the documentation 41 00:01:43,170 --> 00:01:45,629 as well as in human readable form 42 00:01:45,630 --> 00:01:47,469 as well as in machine readable form. 43 00:01:47,470 --> 00:01:50,009 So we can write other tools 44 00:01:50,010 --> 00:01:52,139 that to them useful things 45 00:01:52,140 --> 00:01:53,670 with this kind of devices. 46 00:01:54,810 --> 00:01:56,489 And also from project system. 47 00:01:56,490 --> 00:01:58,649 We have a couple of tools that you can 48 00:01:58,650 --> 00:02:01,109 use to read bitstream 49 00:02:01,110 --> 00:02:03,449 files for those FPGA and 50 00:02:03,450 --> 00:02:05,639 convert those bitstream for 51 00:02:05,640 --> 00:02:08,008 our files into different formats 52 00:02:08,009 --> 00:02:09,240 and vice versa. 53 00:02:10,410 --> 00:02:12,329 The second project I'm going to talk 54 00:02:12,330 --> 00:02:14,759 about this, Arachne, an hour 55 00:02:14,760 --> 00:02:17,519 and a half R hours, a place untruthfully 56 00:02:17,520 --> 00:02:18,809 for the ice. 57 00:02:18,810 --> 00:02:21,059 Forty features, and 58 00:02:21,060 --> 00:02:22,919 it's based on the ice storm 59 00:02:22,920 --> 00:02:24,209 documentation. 60 00:02:24,210 --> 00:02:27,149 So I wrote the ice storm documentation 61 00:02:27,150 --> 00:02:29,699 and then I was lucky enough to 62 00:02:29,700 --> 00:02:30,700 find someone 63 00:02:32,430 --> 00:02:34,589 else's name to write 64 00:02:34,590 --> 00:02:36,959 this our place and wrote to 65 00:02:36,960 --> 00:02:39,149 based on the 66 00:02:39,150 --> 00:02:40,650 documentation I wrote. 67 00:02:42,020 --> 00:02:44,149 The third project I'm going to 68 00:02:44,150 --> 00:02:46,429 talk about is users and 69 00:02:46,430 --> 00:02:48,589 users, actually is my kind of 70 00:02:48,590 --> 00:02:50,869 main project that I'm working 71 00:02:50,870 --> 00:02:53,929 on now for a little bit over three years. 72 00:02:53,930 --> 00:02:56,359 And Yosses uses 73 00:02:56,360 --> 00:02:57,740 a huge project, but 74 00:02:59,090 --> 00:03:01,129 simply said it's a very long synthesis 75 00:03:01,130 --> 00:03:03,199 suite. So when you have hardware 76 00:03:03,200 --> 00:03:05,329 designs that are written in Vallelonga 77 00:03:05,330 --> 00:03:07,729 can use users to synthesize 78 00:03:07,730 --> 00:03:10,879 those designs to Netlist for 79 00:03:10,880 --> 00:03:13,999 a variety of different architectures. 80 00:03:14,000 --> 00:03:16,159 And one of those architectures is the ICE 81 00:03:16,160 --> 00:03:18,400 40 FPGA architecture. 82 00:03:19,730 --> 00:03:21,859 But I also have support for 83 00:03:21,860 --> 00:03:24,229 other FPGA series as they have 84 00:03:24,230 --> 00:03:26,839 support for async synthesis and they also 85 00:03:26,840 --> 00:03:29,299 support various formal verification 86 00:03:29,300 --> 00:03:31,549 flows in users and can 87 00:03:31,550 --> 00:03:33,439 talk about this a little bit. 88 00:03:33,440 --> 00:03:35,020 Not very much. Just just a little bit. 89 00:03:36,760 --> 00:03:39,099 And last but not least, I'm going to talk 90 00:03:39,100 --> 00:03:41,289 about the Ichabod, the 91 00:03:41,290 --> 00:03:43,929 Ichabod and Development 92 00:03:43,930 --> 00:03:46,049 Part featuring the 40 93 00:03:46,050 --> 00:03:48,129 features, and 94 00:03:48,130 --> 00:03:50,499 I'm also showing you a little demo, and 95 00:03:50,500 --> 00:03:52,249 that's this contraption here. 96 00:03:52,250 --> 00:03:53,250 We are going to 97 00:03:54,610 --> 00:03:56,369 use this at the end of the talk. 98 00:03:59,970 --> 00:04:02,549 So this is the floor, 99 00:04:02,550 --> 00:04:03,949 the big overview for the floor, 100 00:04:05,160 --> 00:04:07,259 you see, you 101 00:04:07,260 --> 00:04:10,049 start with the sources 102 00:04:10,050 --> 00:04:11,189 and the synthesis script. 103 00:04:11,190 --> 00:04:13,259 Usually the synthesis script just reads 104 00:04:13,260 --> 00:04:15,899 the very log files and then executes 105 00:04:15,900 --> 00:04:18,299 a few macro commands that do everything 106 00:04:18,300 --> 00:04:20,999 that is necessary to synthesize 107 00:04:21,000 --> 00:04:23,099 for the specified target. 108 00:04:23,100 --> 00:04:25,229 And of course, we are looking at this 109 00:04:25,230 --> 00:04:27,329 for the FPGA here in particular, 110 00:04:27,330 --> 00:04:29,459 the output of of users in 111 00:04:29,460 --> 00:04:31,110 this case is a file 112 00:04:32,190 --> 00:04:34,289 is a very easy a very 113 00:04:34,290 --> 00:04:36,779 simple Netlist format. 114 00:04:36,780 --> 00:04:39,009 And it's one of many format that the user 115 00:04:39,010 --> 00:04:40,859 supports as a spec. 116 00:04:40,860 --> 00:04:42,929 And we we've 117 00:04:42,930 --> 00:04:44,939 made some extensions to the play file 118 00:04:44,940 --> 00:04:47,639 format to enable 119 00:04:47,640 --> 00:04:49,739 the use of additional attributes 120 00:04:49,740 --> 00:04:52,019 on sales and parameters, which is 121 00:04:52,020 --> 00:04:53,969 quite useful when you do, for example, 122 00:04:53,970 --> 00:04:56,189 FPGA synthesis and would like 123 00:04:56,190 --> 00:04:58,499 to have like the load configuration 124 00:04:58,500 --> 00:05:00,599 as part of a 125 00:05:00,600 --> 00:05:03,059 instantiation was a 126 00:05:03,060 --> 00:05:04,109 kind of parameter. 127 00:05:05,870 --> 00:05:08,539 Then we take this Netlist and the cliff 128 00:05:08,540 --> 00:05:10,609 file and we pass it on 129 00:05:10,610 --> 00:05:13,039 to Arachne Pinata 130 00:05:13,040 --> 00:05:15,889 Place and vowed to return the composite 131 00:05:15,890 --> 00:05:18,169 and the OZEKI for a of 132 00:05:18,170 --> 00:05:19,309 additional files. 133 00:05:19,310 --> 00:05:20,659 Namely, we give it the physical 134 00:05:20,660 --> 00:05:23,029 constraints file that specifies 135 00:05:23,030 --> 00:05:25,279 where each pin should go 136 00:05:25,280 --> 00:05:26,539 on the Web. 137 00:05:26,540 --> 00:05:28,879 Each input output of the design should 138 00:05:28,880 --> 00:05:30,829 should go on the device to which it 139 00:05:30,830 --> 00:05:31,879 should map. 140 00:05:33,860 --> 00:05:36,799 You can also specify a 141 00:05:36,800 --> 00:05:38,540 script that tells Arachne 142 00:05:40,250 --> 00:05:42,439 what what strategy to 143 00:05:42,440 --> 00:05:44,509 follow and what what of its 144 00:05:44,510 --> 00:05:46,789 internal passes it to execute 145 00:05:46,790 --> 00:05:47,999 and what order. 146 00:05:49,190 --> 00:05:51,409 The output of that is what I call 147 00:05:51,410 --> 00:05:53,689 an ice storm text file. 148 00:05:53,690 --> 00:05:55,939 This is already a very, very 149 00:05:55,940 --> 00:05:57,239 low level file format. 150 00:05:57,240 --> 00:05:58,730 We will see a short example of that 151 00:05:59,840 --> 00:06:01,939 where you can see for 152 00:06:01,940 --> 00:06:04,129 each individual tile just 153 00:06:04,130 --> 00:06:06,559 asks you a block of zeros and ones 154 00:06:06,560 --> 00:06:08,899 and then, you know, OK, in line eight 155 00:06:08,900 --> 00:06:11,299 and column 13 156 00:06:11,300 --> 00:06:13,459 is a bit that has this or that function. 157 00:06:15,160 --> 00:06:17,649 And lastly, we we passed 158 00:06:17,650 --> 00:06:20,349 this István text file to icepack 159 00:06:20,350 --> 00:06:22,329 and icepack is a very simple tool that 160 00:06:22,330 --> 00:06:24,459 can convert this easy to 161 00:06:24,460 --> 00:06:26,529 read text file into 162 00:06:26,530 --> 00:06:28,689 the binary representation that 163 00:06:28,690 --> 00:06:30,759 must be passed to the FPGA in order to 164 00:06:30,760 --> 00:06:32,320 use this design. 165 00:06:34,950 --> 00:06:37,619 Yeah, so let's look at the 166 00:06:37,620 --> 00:06:39,989 first of those four 167 00:06:39,990 --> 00:06:42,269 project that the first part 168 00:06:42,270 --> 00:06:44,430 of Matak project is done. 169 00:06:46,330 --> 00:06:48,449 First, I think I should give you a little 170 00:06:48,450 --> 00:06:50,969 overview of the E40 FPGA 171 00:06:50,970 --> 00:06:53,339 series, because the eyes for the face 172 00:06:53,340 --> 00:06:55,529 are not very 173 00:06:55,530 --> 00:06:56,489 widely used. 174 00:06:56,490 --> 00:06:58,859 I mean, a lot of people use these devices 175 00:06:58,860 --> 00:07:01,169 or quiara devices, but let 176 00:07:01,170 --> 00:07:03,269 I sort of kind of 177 00:07:03,270 --> 00:07:04,769 kind of niche. 178 00:07:04,770 --> 00:07:06,989 So it's a family of small 179 00:07:06,990 --> 00:07:09,239 FPGA, is the largest one, 180 00:07:09,240 --> 00:07:12,149 has a little bit under 8000 181 00:07:12,150 --> 00:07:14,249 lots and lots of 182 00:07:14,250 --> 00:07:16,379 small for input. 183 00:07:16,380 --> 00:07:19,049 Lots of the FPGA 184 00:07:19,050 --> 00:07:21,179 itself is, of course, a kind of grid 185 00:07:21,180 --> 00:07:23,519 of tiles and the different kind of tiles. 186 00:07:24,720 --> 00:07:26,759 There are logic tiles and those logic 187 00:07:26,760 --> 00:07:28,919 tiles have have eight lookup 188 00:07:28,920 --> 00:07:30,899 tables. And for each of those lookup 189 00:07:30,900 --> 00:07:33,449 tables and optional flip flop and 190 00:07:33,450 --> 00:07:35,639 a carry chain logic 191 00:07:35,640 --> 00:07:37,739 that you can use optionally, 192 00:07:37,740 --> 00:07:39,989 there are also some tiles for four block 193 00:07:39,990 --> 00:07:40,979 memory. 194 00:07:40,980 --> 00:07:42,419 They are always coming past. 195 00:07:42,420 --> 00:07:44,849 There's always Ramsbottom 196 00:07:44,850 --> 00:07:46,949 tile in the top tile 197 00:07:46,950 --> 00:07:49,139 and a bottom tile in the top tile. 198 00:07:49,140 --> 00:07:51,269 Together they form 199 00:07:51,270 --> 00:07:53,129 a four kilobyte astron. 200 00:07:53,130 --> 00:07:55,649 And of course there are all tiles 201 00:07:55,650 --> 00:07:57,989 on the edges of 202 00:07:57,990 --> 00:08:00,179 of the scripts that connect 203 00:08:00,180 --> 00:08:02,999 to the programable eye opens, but 204 00:08:03,000 --> 00:08:05,969 also provide the infrastructure necessary 205 00:08:05,970 --> 00:08:08,219 to connect the 206 00:08:08,220 --> 00:08:10,949 FPGA logic with other resources 207 00:08:10,950 --> 00:08:13,079 on the chip like Nelsonville overnight. 208 00:08:14,590 --> 00:08:16,659 A nice thing about 209 00:08:16,660 --> 00:08:18,819 ICE 40 is that they come in quite 210 00:08:18,820 --> 00:08:20,979 reasonable packages, so then you would 211 00:08:20,980 --> 00:08:23,709 like to make your own boards that 212 00:08:23,710 --> 00:08:26,019 can be quite a hassle to work with 213 00:08:26,020 --> 00:08:27,909 biodegrades arrays and stuff like that. 214 00:08:27,910 --> 00:08:30,789 But the ICE 40 features 215 00:08:30,790 --> 00:08:32,979 come in in packages like 216 00:08:32,980 --> 00:08:34,599 144 PIN tulku. 217 00:08:34,600 --> 00:08:36,819 Of that, you can even fold 218 00:08:36,820 --> 00:08:37,940 up a hand if you have to. 219 00:08:39,400 --> 00:08:40,899 And all of them are very cheap 220 00:08:40,900 --> 00:08:43,178 development boards available from Lettice 221 00:08:43,179 --> 00:08:46,029 directly for for this kind of FPGA. 222 00:08:46,030 --> 00:08:48,219 The lettuce I stick cost 223 00:08:48,220 --> 00:08:49,659 less than twenty five dollars. 224 00:08:49,660 --> 00:08:51,759 So it's really affordable for 225 00:08:51,760 --> 00:08:53,979 someone who just would like to 226 00:08:53,980 --> 00:08:56,229 experiment with it and have a quick go 227 00:08:56,230 --> 00:08:57,429 at it. 228 00:08:57,430 --> 00:08:59,559 Also, if you would like to do some 229 00:08:59,560 --> 00:09:01,689 low level stuff and are afraid of 230 00:09:01,690 --> 00:09:03,969 maybe breaking your dashboard by 231 00:09:03,970 --> 00:09:06,159 by fiddling with the configuration, it's 232 00:09:06,160 --> 00:09:08,259 manually, then it's 233 00:09:08,260 --> 00:09:10,149 quite nice to have that part in this 234 00:09:10,150 --> 00:09:11,469 price range. 235 00:09:11,470 --> 00:09:12,470 Nothing is. 236 00:09:14,280 --> 00:09:16,769 Yeah, Americans can simply replace 237 00:09:16,770 --> 00:09:17,770 it. 238 00:09:18,990 --> 00:09:21,149 So in summary, the FBI looks a little 239 00:09:21,150 --> 00:09:23,459 bit like that. We have this, this, 240 00:09:23,460 --> 00:09:26,099 this this group of of of 241 00:09:26,100 --> 00:09:27,689 these program logic blocks. 242 00:09:27,690 --> 00:09:29,789 This are the logic tiles. 243 00:09:29,790 --> 00:09:32,399 We have some some memory tiles that span 244 00:09:32,400 --> 00:09:34,979 two rows. 245 00:09:34,980 --> 00:09:37,409 And you have to add all wall tiles 246 00:09:37,410 --> 00:09:39,509 on the on the edges. 247 00:09:39,510 --> 00:09:40,799 And then in the middle of that slide, we 248 00:09:40,800 --> 00:09:43,139 have a more detailed look into one 249 00:09:43,140 --> 00:09:44,669 of these logic tiles 250 00:09:46,200 --> 00:09:48,419 where we see you have these eight 251 00:09:48,420 --> 00:09:49,799 flip flops, eight 252 00:09:51,150 --> 00:09:53,819 Khari chain elements 253 00:09:53,820 --> 00:09:54,950 and eight lookup tables. 254 00:09:56,280 --> 00:09:58,469 This is also blowing up here 255 00:09:58,470 --> 00:09:59,909 so they can see it in more detail. 256 00:09:59,910 --> 00:10:01,380 However, this is still just 257 00:10:04,800 --> 00:10:06,149 it's still missing stuff. 258 00:10:06,150 --> 00:10:08,339 For example, there is a connection that 259 00:10:08,340 --> 00:10:10,949 goes directly from one output 260 00:10:10,950 --> 00:10:13,109 to the second 261 00:10:13,110 --> 00:10:14,399 input of the next 262 00:10:16,500 --> 00:10:18,779 look and look at people in this chain 263 00:10:18,780 --> 00:10:20,909 bypassing the flip flop. 264 00:10:22,960 --> 00:10:24,729 Yeah, and the bottom right, you see, this 265 00:10:24,730 --> 00:10:26,859 is the spot that you can buy from 266 00:10:26,860 --> 00:10:29,049 that is for under twenty five 267 00:10:29,050 --> 00:10:30,789 dollars, I think it costs twenty five 268 00:10:30,790 --> 00:10:33,099 dollars from let's put it on the twenty 269 00:10:33,100 --> 00:10:34,100 five dollars. 270 00:10:36,890 --> 00:10:39,019 Good service project, Ice Time, we 271 00:10:39,020 --> 00:10:41,079 had a detailed look at this FPGA 272 00:10:41,080 --> 00:10:43,339 sound, we documented 273 00:10:43,340 --> 00:10:45,499 the bitstream format and we wrote 274 00:10:45,500 --> 00:10:47,779 this low level tools that can be used to 275 00:10:47,780 --> 00:10:50,089 work with the streams. 276 00:10:50,090 --> 00:10:52,249 And we also defined a very simple text 277 00:10:52,250 --> 00:10:54,319 file that can be used to just 278 00:10:54,320 --> 00:10:56,569 specify each and every individual 279 00:10:56,570 --> 00:10:58,429 bit in the configuration. 280 00:10:58,430 --> 00:11:00,199 And on the right on this slide, you see a 281 00:11:00,200 --> 00:11:02,269 little excerpt of what this 282 00:11:02,270 --> 00:11:03,559 text file looked like. 283 00:11:03,560 --> 00:11:05,959 So you have your logic 284 00:11:05,960 --> 00:11:06,859 Title nine nine. 285 00:11:06,860 --> 00:11:08,029 And these are, of course, the 286 00:11:08,030 --> 00:11:10,039 coordinates. And then you just have this 287 00:11:10,040 --> 00:11:12,259 this block of ones 288 00:11:12,260 --> 00:11:14,569 and zeros. And then you can when you 289 00:11:14,570 --> 00:11:16,999 when you look up the documentation online 290 00:11:17,000 --> 00:11:19,249 that we provided and you can 291 00:11:19,250 --> 00:11:21,709 decipher that and say, OK, this 292 00:11:21,710 --> 00:11:23,329 is set because it has this function at 293 00:11:23,330 --> 00:11:25,459 this kind of makes sense for what this 294 00:11:25,460 --> 00:11:26,460 configuration does. 295 00:11:28,320 --> 00:11:30,389 So with the tools we can 296 00:11:30,390 --> 00:11:31,979 convert between the text files and the 297 00:11:31,980 --> 00:11:34,619 binary files, and 298 00:11:34,620 --> 00:11:37,049 we can also do a lot of other interesting 299 00:11:37,050 --> 00:11:38,819 stuff, for example, you can take one of 300 00:11:38,820 --> 00:11:40,979 those text files and convert it back 301 00:11:40,980 --> 00:11:43,589 into a behavioral model. 302 00:11:43,590 --> 00:11:45,419 And actually, when I released this 303 00:11:45,420 --> 00:11:47,279 feature the first time, I got quite some 304 00:11:47,280 --> 00:11:49,409 hate mail from people who thought I want 305 00:11:49,410 --> 00:11:50,879 to steal their IP or something. 306 00:11:52,730 --> 00:11:54,919 You can also create timing Netlist 307 00:11:54,920 --> 00:11:57,029 from this bitstream directly. 308 00:11:57,030 --> 00:11:59,389 However, this is under construction, 309 00:11:59,390 --> 00:12:01,609 it's almost done, but not 310 00:12:01,610 --> 00:12:02,850 quite yet. 311 00:12:03,890 --> 00:12:06,049 The reason why we are doing things like 312 00:12:06,050 --> 00:12:08,299 that always on this low level 313 00:12:08,300 --> 00:12:10,519 bitstream format is because 314 00:12:10,520 --> 00:12:12,739 we can create these files from our own 315 00:12:12,740 --> 00:12:15,049 floor, but they can also created for 316 00:12:15,050 --> 00:12:17,269 the bitstream files generated 317 00:12:17,270 --> 00:12:19,009 by letters flow. 318 00:12:19,010 --> 00:12:21,109 So it's very easy to verify 319 00:12:21,110 --> 00:12:23,839 if our interpretation of the 320 00:12:23,840 --> 00:12:26,149 of the bitstream is correct or just 321 00:12:26,150 --> 00:12:27,950 create random badenoch designs 322 00:12:29,420 --> 00:12:31,519 passing through the letters flow, then 323 00:12:31,520 --> 00:12:33,439 convert the output back into something 324 00:12:33,440 --> 00:12:35,509 that is behaviorally analog and then use 325 00:12:35,510 --> 00:12:37,309 something like the formal verification 326 00:12:37,310 --> 00:12:39,919 features in users to check. 327 00:12:39,920 --> 00:12:42,079 If we started with 328 00:12:42,080 --> 00:12:44,389 a.. Figured out at the end a formally 329 00:12:44,390 --> 00:12:45,390 equivalent. 330 00:12:49,490 --> 00:12:51,619 So you can 331 00:12:51,620 --> 00:12:54,139 go to the latest ice storm and 332 00:12:54,140 --> 00:12:55,609 browse the documentation. 333 00:12:55,610 --> 00:12:57,709 I wrote a little 334 00:12:57,710 --> 00:13:00,129 bit of warning here, and 335 00:13:00,130 --> 00:13:01,789 it's a reference that not it's not like 336 00:13:01,790 --> 00:13:03,389 an introductory textbook. 337 00:13:03,390 --> 00:13:05,509 So if you don't 338 00:13:05,510 --> 00:13:08,209 know anything about how FPGA is working 339 00:13:08,210 --> 00:13:10,819 internally, it might be a 340 00:13:10,820 --> 00:13:11,820 hard read, 341 00:13:13,070 --> 00:13:14,749 although it's actually not very well 342 00:13:14,750 --> 00:13:17,089 structured, unfortunately. 343 00:13:17,090 --> 00:13:18,199 But it's not very long. 344 00:13:18,200 --> 00:13:19,489 It's just a few pages of my 345 00:13:19,490 --> 00:13:21,109 recommendation. If you really would like 346 00:13:21,110 --> 00:13:23,719 to know how this FPGA spoke 347 00:13:23,720 --> 00:13:25,999 and what the individual bit means is 348 00:13:26,000 --> 00:13:28,009 to just read the entire thing once and 349 00:13:28,010 --> 00:13:30,169 then you have an overview 350 00:13:30,170 --> 00:13:31,129 of what is. 351 00:13:31,130 --> 00:13:32,779 And for example, most of the 352 00:13:32,780 --> 00:13:34,849 interconnectedness explains in the on 353 00:13:34,850 --> 00:13:37,039 the page for the logic types and 354 00:13:37,040 --> 00:13:39,859 things like like listen to your Burnetts 355 00:13:39,860 --> 00:13:42,199 explained on the on the page to 356 00:13:42,200 --> 00:13:43,759 cover the details. 357 00:13:44,810 --> 00:13:46,789 But it's really small and you can can 358 00:13:46,790 --> 00:13:48,919 read it in maybe an hour or two. 359 00:13:48,920 --> 00:13:50,460 So it's, I think, not so bad. 360 00:13:51,860 --> 00:13:54,739 So the things provided by 361 00:13:54,740 --> 00:13:57,549 my project besides the 362 00:13:57,550 --> 00:13:59,209 the actual tools, the documentation 363 00:13:59,210 --> 00:14:01,639 provided, this is a written 364 00:14:01,640 --> 00:14:04,069 documentation that gives you an overview. 365 00:14:04,070 --> 00:14:06,229 Then there is an auto generated HTML 366 00:14:06,230 --> 00:14:08,359 documentation that 367 00:14:08,360 --> 00:14:10,459 gives you the reference, what each 368 00:14:10,460 --> 00:14:12,289 bit exactly means. 369 00:14:12,290 --> 00:14:14,389 And there is also an auto generated USSI 370 00:14:14,390 --> 00:14:17,029 database that can be used in other tools 371 00:14:17,030 --> 00:14:19,279 like Arachne to 372 00:14:19,280 --> 00:14:22,459 do something with this kind of FPGA. 373 00:14:22,460 --> 00:14:24,859 And you have a couple of screenshots from 374 00:14:24,860 --> 00:14:26,989 this documentation. 375 00:14:26,990 --> 00:14:29,149 So on the on the lower left, 376 00:14:29,150 --> 00:14:30,499 you have some of the written 377 00:14:30,500 --> 00:14:32,539 documentation that covers. 378 00:14:32,540 --> 00:14:34,729 This is actually from the from the I o 379 00:14:34,730 --> 00:14:37,129 tile. And you see the column 380 00:14:37,130 --> 00:14:39,229 PAFA control bits that 381 00:14:39,230 --> 00:14:40,669 are used for the overnight's and stuff 382 00:14:40,670 --> 00:14:41,949 like that is documented here. 383 00:14:43,190 --> 00:14:45,979 Then the two 384 00:14:45,980 --> 00:14:47,779 screenshots with this this, this 385 00:14:48,920 --> 00:14:51,229 wonderfully colored table, 386 00:14:51,230 --> 00:14:54,109 this the automated generated 387 00:14:54,110 --> 00:14:56,179 HTML documentation where we 388 00:14:56,180 --> 00:14:58,039 document the function of each and every 389 00:14:58,040 --> 00:15:00,169 individual bit, and most 390 00:15:00,170 --> 00:15:02,479 of them in more than than just 391 00:15:02,480 --> 00:15:04,159 one way. So we have 392 00:15:05,480 --> 00:15:07,579 in this case some some matrices 393 00:15:07,580 --> 00:15:09,979 that can tell us which nets 394 00:15:09,980 --> 00:15:11,509 can be connected to each other. 395 00:15:11,510 --> 00:15:13,699 That and what bits are 396 00:15:13,700 --> 00:15:15,079 used for that. 397 00:15:15,080 --> 00:15:17,210 And here on the apparatus, actually, see 398 00:15:18,280 --> 00:15:20,780 for for one logic, Tildy, the entire 399 00:15:21,980 --> 00:15:23,899 collection of bits, we have a reverse 400 00:15:23,900 --> 00:15:25,129 engineer. 401 00:15:25,130 --> 00:15:26,179 So you see there are some 402 00:15:27,200 --> 00:15:30,019 you see there are some some gray areas. 403 00:15:30,020 --> 00:15:32,119 And as far as I 404 00:15:32,120 --> 00:15:34,039 can tell, it's not the things that I have 405 00:15:34,040 --> 00:15:36,169 missed, but these bits are just not 406 00:15:36,170 --> 00:15:37,170 used. 407 00:15:39,580 --> 00:15:41,889 I can't be sure, of course, but I didn't 408 00:15:41,890 --> 00:15:44,289 manage to create any 409 00:15:44,290 --> 00:15:45,999 design that would use those bits, so I 410 00:15:46,000 --> 00:15:48,099 think it's a pretty fair guess that 411 00:15:48,100 --> 00:15:49,329 they actually are unused. 412 00:15:49,330 --> 00:15:51,639 And on the on the bottom right, you see 413 00:15:51,640 --> 00:15:55,089 a part of the interconnect documentation 414 00:15:55,090 --> 00:15:57,219 and you can can see things like 415 00:15:57,220 --> 00:15:59,319 this. This interconnect 416 00:15:59,320 --> 00:16:01,599 lines are crossed out and 417 00:16:01,600 --> 00:16:02,529 stuff like that. 418 00:16:02,530 --> 00:16:04,899 So it took us quite a while 419 00:16:04,900 --> 00:16:07,260 to to figure out all these details. 420 00:16:08,630 --> 00:16:10,699 Yeah, so that's that's project I assume 421 00:16:10,700 --> 00:16:11,869 that's the low level stuff. 422 00:16:13,160 --> 00:16:14,809 And of course, it's very interesting to 423 00:16:14,810 --> 00:16:16,969 just see how the FPGA works and to 424 00:16:16,970 --> 00:16:19,369 know what each and every individual does. 425 00:16:19,370 --> 00:16:21,199 But this doesn't really give us something 426 00:16:21,200 --> 00:16:23,959 that we can can use for like like 427 00:16:23,960 --> 00:16:26,149 everyday design work with with 428 00:16:26,150 --> 00:16:27,150 FPGA. 429 00:16:28,800 --> 00:16:31,169 So part two of 430 00:16:31,170 --> 00:16:32,519 this is the place untruthful 431 00:16:33,600 --> 00:16:35,759 that Cottonseed wrote 432 00:16:35,760 --> 00:16:38,549 this now takes this place Netlist 433 00:16:38,550 --> 00:16:40,919 and convert it into one of those text 434 00:16:40,920 --> 00:16:41,920 files. 435 00:16:42,570 --> 00:16:44,939 So it performs essentially 436 00:16:44,940 --> 00:16:47,189 this operations here, it 437 00:16:47,190 --> 00:16:49,050 instantiates I oversells. 438 00:16:50,220 --> 00:16:52,559 And this is more like a convenience 439 00:16:52,560 --> 00:16:54,089 feature, but it's something that is quite 440 00:16:54,090 --> 00:16:56,279 useful for our place and throughout 441 00:16:56,280 --> 00:16:57,959 low level implementation tools to do 442 00:16:57,960 --> 00:17:00,449 something like that, it packs 443 00:17:00,450 --> 00:17:02,699 looks and Carol Logic's and flipflop 444 00:17:02,700 --> 00:17:05,068 instances into isolated logic 445 00:17:05,069 --> 00:17:08,009 cells because the architecture Netlist 446 00:17:08,010 --> 00:17:10,169 has individual lookup tables and 447 00:17:10,170 --> 00:17:12,629 carry logic blocks and flip flops 448 00:17:12,630 --> 00:17:14,999 and we need to figure out how 449 00:17:15,000 --> 00:17:17,219 we can fit them into 450 00:17:17,220 --> 00:17:18,390 this logic cells, 451 00:17:19,680 --> 00:17:21,779 then replace the design. 452 00:17:21,780 --> 00:17:24,358 This is currently done by simulated 453 00:17:24,359 --> 00:17:26,549 annealing only, but we are 454 00:17:26,550 --> 00:17:28,649 walking on the floor that that 455 00:17:28,650 --> 00:17:30,749 would use like a 456 00:17:30,750 --> 00:17:32,309 first step that. 457 00:17:36,440 --> 00:17:38,329 That does an analytical placement and 458 00:17:38,330 --> 00:17:40,129 then we refine it using simulated 459 00:17:40,130 --> 00:17:42,109 annealing, then, of course, throughout 460 00:17:42,110 --> 00:17:45,409 the design and then it comes to the FPGA 461 00:17:45,410 --> 00:17:46,410 config. 462 00:17:47,030 --> 00:17:49,159 So how does this input Netlist 463 00:17:49,160 --> 00:17:52,429 format will look like this display file? 464 00:17:52,430 --> 00:17:54,499 We use the same cell types that 465 00:17:54,500 --> 00:17:56,569 are used for the by the 466 00:17:56,570 --> 00:17:57,889 latest twist themselves. 467 00:17:57,890 --> 00:17:59,749 So we will stick to the ice for the 468 00:17:59,750 --> 00:18:01,879 technology library, which 469 00:18:01,880 --> 00:18:04,069 allows us to to mix our 470 00:18:04,070 --> 00:18:06,069 own toolchain with the letters to change 471 00:18:06,070 --> 00:18:08,419 and for example, use use our front 472 00:18:08,420 --> 00:18:09,769 end and then go into the letters 473 00:18:09,770 --> 00:18:10,930 background or vice versa. 474 00:18:13,590 --> 00:18:15,529 Cliff is a pretty easy file format, and 475 00:18:15,530 --> 00:18:17,629 you see a simple example 476 00:18:17,630 --> 00:18:19,039 here. 477 00:18:19,040 --> 00:18:20,890 Model is just a statement for. 478 00:18:22,420 --> 00:18:24,669 Lefkow is a model, but 479 00:18:24,670 --> 00:18:26,109 you would see a model 480 00:18:27,580 --> 00:18:29,409 and then you have a list of inputs and 481 00:18:29,410 --> 00:18:31,509 outputs, every nets that are used 482 00:18:31,510 --> 00:18:33,279 but not delivered as inputs and outputs 483 00:18:33,280 --> 00:18:34,420 are just internal wires. 484 00:18:35,530 --> 00:18:37,479 And in this case, the entire design is 485 00:18:37,480 --> 00:18:40,149 just a simple lookup table, 486 00:18:40,150 --> 00:18:42,489 essentially spelled out for 487 00:18:42,490 --> 00:18:44,889 with this for inputs and outputs. 488 00:18:44,890 --> 00:18:47,409 And here you see are nonstandard 489 00:18:47,410 --> 00:18:50,199 statement that is used to set the 490 00:18:50,200 --> 00:18:52,359 lookup table for for this 491 00:18:52,360 --> 00:18:54,550 particular lot, for instance. 492 00:18:56,620 --> 00:18:58,959 But it can also put 493 00:18:58,960 --> 00:19:01,069 additional input files into the ice 494 00:19:01,070 --> 00:19:03,609 storm flow, for example, you can 495 00:19:03,610 --> 00:19:05,199 give it the physical constraints file, as 496 00:19:05,200 --> 00:19:07,539 I mentioned already, that is primarily 497 00:19:07,540 --> 00:19:08,979 used for your placement. 498 00:19:08,980 --> 00:19:11,169 And once again, we try to 499 00:19:11,170 --> 00:19:13,569 do something that looks very similar to 500 00:19:13,570 --> 00:19:15,219 the file formats used by the latest 501 00:19:15,220 --> 00:19:17,479 tools. So it's easy to 502 00:19:17,480 --> 00:19:19,629 to switch between back and forth between 503 00:19:19,630 --> 00:19:21,460 our two tuition and the latest, which 504 00:19:22,540 --> 00:19:24,379 you can also use a place and throughout 505 00:19:24,380 --> 00:19:26,529 script. This is more experimental feature 506 00:19:26,530 --> 00:19:28,999 that is in development right now. 507 00:19:29,000 --> 00:19:31,809 They can manually 508 00:19:31,810 --> 00:19:33,969 specify what steps should 509 00:19:33,970 --> 00:19:36,099 be taken in which order and also 510 00:19:36,100 --> 00:19:38,379 give the individual additional 511 00:19:38,380 --> 00:19:39,699 parameters. 512 00:19:39,700 --> 00:19:42,219 And with that, we have already 513 00:19:42,220 --> 00:19:44,359 an experimental flow of very used 514 00:19:44,360 --> 00:19:46,599 to analytical plays and uses together 515 00:19:46,600 --> 00:19:47,919 with Arachne. 516 00:19:47,920 --> 00:19:49,599 But that's not actually what I would like 517 00:19:49,600 --> 00:19:52,089 to do in the analytical placement, 518 00:19:52,090 --> 00:19:53,949 because the analytical placement uses 519 00:19:53,950 --> 00:19:56,159 doesn't really know how 520 00:19:56,160 --> 00:19:58,239 the speech looks like 521 00:19:58,240 --> 00:20:00,459 and that there are only certain places 522 00:20:00,460 --> 00:20:02,439 where tile can go, for example. 523 00:20:05,700 --> 00:20:07,679 The output format of the panel on the 524 00:20:07,680 --> 00:20:10,529 other side of this system, 525 00:20:10,530 --> 00:20:12,719 ASCII files, and as I've said, they can't 526 00:20:12,720 --> 00:20:13,720 be converted to 527 00:20:14,820 --> 00:20:16,289 the things that you would like to do with 528 00:20:16,290 --> 00:20:18,359 them, with the some 529 00:20:18,360 --> 00:20:19,649 low level tools. 530 00:20:19,650 --> 00:20:21,269 But of course, you can also create 531 00:20:21,270 --> 00:20:23,789 additional outputs like placement 532 00:20:23,790 --> 00:20:26,069 file that contains all 533 00:20:26,070 --> 00:20:27,449 the placement of the generated 534 00:20:27,450 --> 00:20:30,249 automatically during a placement 535 00:20:30,250 --> 00:20:32,429 or that list of, for 536 00:20:32,430 --> 00:20:35,249 example, the PECT design, 537 00:20:35,250 --> 00:20:36,719 because this is something that you might 538 00:20:36,720 --> 00:20:37,799 want to investigate. 539 00:20:39,440 --> 00:20:41,629 So this is the second 540 00:20:41,630 --> 00:20:44,149 part of our Floreana. 541 00:20:44,150 --> 00:20:46,309 Now we can take 542 00:20:46,310 --> 00:20:47,989 a technology Netlist and actually 543 00:20:47,990 --> 00:20:50,419 implement it on the 544 00:20:50,420 --> 00:20:52,789 the the 545 00:20:52,790 --> 00:20:54,019 chip. So 546 00:20:55,340 --> 00:20:57,199 theoretically, we could already create 547 00:20:57,200 --> 00:20:59,179 very minimalist designs. 548 00:20:59,180 --> 00:21:01,249 But it's not not not 549 00:21:01,250 --> 00:21:02,750 how you would like to do it. 550 00:21:03,950 --> 00:21:06,259 So in the third part, we're going 551 00:21:06,260 --> 00:21:08,229 to look at users and users, as I've said, 552 00:21:08,230 --> 00:21:10,009 is my my main project. 553 00:21:10,010 --> 00:21:12,139 It's the tool that can 554 00:21:12,140 --> 00:21:14,239 actually take HDL designs written in 555 00:21:14,240 --> 00:21:16,369 the airlock and convert them to 556 00:21:16,370 --> 00:21:18,529 whatever you would like to use in the 557 00:21:18,530 --> 00:21:19,530 end. 558 00:21:20,060 --> 00:21:22,129 So this is a small excerpt of 559 00:21:22,130 --> 00:21:23,509 what you can do with yourself. 560 00:21:23,510 --> 00:21:25,399 You can read various file formats and 561 00:21:25,400 --> 00:21:27,499 most importantly, you can read 562 00:21:27,500 --> 00:21:29,719 via Hallock. And in this case, the analog 563 00:21:29,720 --> 00:21:32,089 is pretty much everything from the analog 564 00:21:32,090 --> 00:21:33,379 2005. 565 00:21:33,380 --> 00:21:35,449 So it's 566 00:21:35,450 --> 00:21:36,559 pretty much up to date. 567 00:21:39,470 --> 00:21:41,149 However, as you can see, there is no 568 00:21:41,150 --> 00:21:43,329 visible front and at the moment 569 00:21:43,330 --> 00:21:45,379 are people who are saying they would like 570 00:21:45,380 --> 00:21:46,279 to work on that. 571 00:21:46,280 --> 00:21:48,769 And I am very curious 572 00:21:48,770 --> 00:21:50,839 to find out what what 573 00:21:50,840 --> 00:21:52,069 we'll see in a year or so. 574 00:21:53,510 --> 00:21:55,489 You can write various file formats. 575 00:21:55,490 --> 00:21:57,649 Of course, you can write off that list, 576 00:21:57,650 --> 00:21:59,719 which can be interesting for things like 577 00:21:59,720 --> 00:22:01,549 post synthesis simulation. 578 00:22:01,550 --> 00:22:03,499 But you can also write Beliefnet list. 579 00:22:03,500 --> 00:22:05,599 You can write it if not list, which 580 00:22:05,600 --> 00:22:07,669 is very important if you would like to 581 00:22:07,670 --> 00:22:09,799 go into a commercial account, because 582 00:22:09,800 --> 00:22:12,169 they usually use it as 583 00:22:12,170 --> 00:22:14,239 an interest exchange format and some 584 00:22:14,240 --> 00:22:16,399 other format, you can 585 00:22:16,400 --> 00:22:18,469 of course, perform RTL 586 00:22:18,470 --> 00:22:20,749 synthesis and also logic 587 00:22:20,750 --> 00:22:21,799 optimization. 588 00:22:21,800 --> 00:22:23,869 Some of the optimization is done and uses 589 00:22:23,870 --> 00:22:25,969 directly and some of the optimization 590 00:22:25,970 --> 00:22:28,129 uses an external tool from the 591 00:22:28,130 --> 00:22:30,199 university called ABC, which is 592 00:22:30,200 --> 00:22:32,239 used for like low level logic 593 00:22:32,240 --> 00:22:33,240 optimization. 594 00:22:35,120 --> 00:22:37,819 And you can, of course, map the science 595 00:22:37,820 --> 00:22:39,889 to target architecture like 596 00:22:39,890 --> 00:22:42,319 certain FPGA architect architectures 597 00:22:42,320 --> 00:22:44,389 or Excel libraries, and 598 00:22:44,390 --> 00:22:46,399 you can also perform far more 599 00:22:46,400 --> 00:22:49,099 verifications, which is 600 00:22:49,100 --> 00:22:51,319 actually the thing I maybe spent most 601 00:22:51,320 --> 00:22:52,930 time on working. 602 00:22:54,620 --> 00:22:57,019 Some have said that uses something 603 00:22:57,020 --> 00:22:59,419 like LGM for hardware. 604 00:22:59,420 --> 00:23:01,819 I really like this this idea 605 00:23:01,820 --> 00:23:03,259 and I like this analogy. 606 00:23:03,260 --> 00:23:05,809 But there are a couple of 607 00:23:05,810 --> 00:23:08,269 projects at the moment that try to become 608 00:23:08,270 --> 00:23:10,369 the LVM father, 609 00:23:10,370 --> 00:23:12,010 so I can't really claim the title yet. 610 00:23:14,670 --> 00:23:16,529 So what what kind of laws to really 611 00:23:16,530 --> 00:23:18,599 exist? Of course, there exist many 612 00:23:18,600 --> 00:23:20,129 more laws that are implemented with 613 00:23:20,130 --> 00:23:22,499 users, but most of them are like 614 00:23:22,500 --> 00:23:24,689 one one person 615 00:23:24,690 --> 00:23:26,759 building a custom floor, which is part of 616 00:23:26,760 --> 00:23:29,219 the season's work or something like that. 617 00:23:29,220 --> 00:23:31,859 So these are the floors that 618 00:23:31,860 --> 00:23:34,379 are like more general and something 619 00:23:34,380 --> 00:23:36,989 that that that you actually 620 00:23:36,990 --> 00:23:38,099 might want to use. 621 00:23:38,100 --> 00:23:40,259 As it is, there 622 00:23:40,260 --> 00:23:43,339 are two floors that use yourselves 623 00:23:43,340 --> 00:23:45,719 as front end desk floor. 624 00:23:45,720 --> 00:23:47,669 And there's is, too. 625 00:23:47,670 --> 00:23:49,739 And both of them have been 626 00:23:49,740 --> 00:23:51,929 already used to tape out chips 627 00:23:51,930 --> 00:23:52,949 for Q4. 628 00:23:52,950 --> 00:23:55,119 I also know that people have taped 629 00:23:55,120 --> 00:23:56,369 commercial ships with that. 630 00:23:57,430 --> 00:23:59,339 So this is something that is actually in 631 00:23:59,340 --> 00:24:01,679 use and it's not like a thought 632 00:24:01,680 --> 00:24:03,749 experiment. And theoretically, they could 633 00:24:03,750 --> 00:24:05,729 it's actually done. 634 00:24:05,730 --> 00:24:07,169 Then, of course, there is the synthesis 635 00:24:07,170 --> 00:24:09,299 files for the FPGA, 636 00:24:09,300 --> 00:24:11,399 which is the floor I'm talking about 637 00:24:11,400 --> 00:24:12,549 right now. 638 00:24:12,550 --> 00:24:14,639 And then there is a floor for exiling 639 00:24:14,640 --> 00:24:16,499 seven series FPGA. 640 00:24:16,500 --> 00:24:18,569 But with that flow, we don't have 641 00:24:18,570 --> 00:24:20,819 any open source implementation backend 642 00:24:20,820 --> 00:24:22,739 to do things like place handwrote. 643 00:24:22,740 --> 00:24:24,989 So you could use 644 00:24:24,990 --> 00:24:26,999 users to do the synthesis, but then you 645 00:24:27,000 --> 00:24:28,769 would still need to use something like 646 00:24:28,770 --> 00:24:31,169 Tydings Movado to to do the actual 647 00:24:31,170 --> 00:24:32,170 implementation. 648 00:24:33,750 --> 00:24:35,819 And of course, there are a few former 649 00:24:35,820 --> 00:24:38,879 verification floors, and 650 00:24:38,880 --> 00:24:40,949 I think the most interesting 651 00:24:40,950 --> 00:24:42,239 one is yours as S.A. 652 00:24:42,240 --> 00:24:45,479 BMC that used 653 00:24:45,480 --> 00:24:47,879 to perform former 654 00:24:47,880 --> 00:24:50,459 verifications using standalone 655 00:24:50,460 --> 00:24:52,769 S.A. solvers by writing 656 00:24:52,770 --> 00:24:54,599 files in S.A. 657 00:24:54,600 --> 00:24:56,789 to format and doesn't to is the format 658 00:24:56,790 --> 00:24:59,099 that is used for the competitions before 659 00:24:59,100 --> 00:25:00,009 asanti solver. 660 00:25:00,010 --> 00:25:02,309 So this means you have no vendor 661 00:25:02,310 --> 00:25:04,409 lock in whatsoever because 662 00:25:04,410 --> 00:25:05,419 every S.A.S. 663 00:25:05,420 --> 00:25:07,739 solver that is going to be written 664 00:25:07,740 --> 00:25:09,719 will support the Assante to file format 665 00:25:09,720 --> 00:25:11,409 because they want to compete in these 666 00:25:11,410 --> 00:25:12,410 competitions. 667 00:25:14,150 --> 00:25:16,429 So what does Yosses syntheses 668 00:25:16,430 --> 00:25:18,559 script look like and 669 00:25:18,560 --> 00:25:19,790 that something like this here 670 00:25:20,930 --> 00:25:23,119 you have a usually generic part 671 00:25:23,120 --> 00:25:26,539 that is just read this design files 672 00:25:26,540 --> 00:25:28,759 and then some kind of synthesis 673 00:25:28,760 --> 00:25:30,869 comment that is here, 674 00:25:30,870 --> 00:25:32,809 the very generic comment. 675 00:25:33,860 --> 00:25:36,349 And then you have a target specific part 676 00:25:36,350 --> 00:25:38,089 that does the mapping to the target 677 00:25:38,090 --> 00:25:39,679 architecture in this case. 678 00:25:39,680 --> 00:25:41,300 And they sell library. 679 00:25:42,890 --> 00:25:45,139 But, of course, this this looks very much 680 00:25:45,140 --> 00:25:47,029 like it looks when when you're looking to 681 00:25:47,030 --> 00:25:49,399 commercial lasic floors, 682 00:25:49,400 --> 00:25:51,649 they usually look quite similar that 683 00:25:51,650 --> 00:25:53,329 you have something like a script and it 684 00:25:53,330 --> 00:25:55,489 reads a few files and 685 00:25:55,490 --> 00:25:57,619 then it calls one command that does 686 00:25:57,620 --> 00:25:58,899 the magic synthesis part, 687 00:25:59,910 --> 00:26:02,059 but then uses this command is 688 00:26:02,060 --> 00:26:04,249 actually a script itself that is just 689 00:26:04,250 --> 00:26:06,049 a sequence of other comments. 690 00:26:06,050 --> 00:26:08,179 And then you look into the health message 691 00:26:08,180 --> 00:26:10,279 for the CENTCOM and then you see 692 00:26:10,280 --> 00:26:12,499 this, the script that is actually used 693 00:26:12,500 --> 00:26:13,669 behind the scenes. 694 00:26:13,670 --> 00:26:16,099 And some of those comments like Pork 695 00:26:16,100 --> 00:26:18,679 Opt or FSM or memory 696 00:26:18,680 --> 00:26:20,779 are themselves just sequences of 697 00:26:20,780 --> 00:26:21,719 other comments. 698 00:26:21,720 --> 00:26:23,959 So it's quite easy to to 699 00:26:23,960 --> 00:26:26,239 look at this and actually understand what 700 00:26:26,240 --> 00:26:28,459 what steps are taken in sequence 701 00:26:28,460 --> 00:26:30,589 to a high level description of 702 00:26:30,590 --> 00:26:33,169 a design into a low level necklaced 703 00:26:33,170 --> 00:26:35,479 for the given target architecture and 704 00:26:35,480 --> 00:26:37,249 is, of course, also possible to do things 705 00:26:37,250 --> 00:26:39,529 like stop synthesis at any given 706 00:26:39,530 --> 00:26:41,749 point here, and then dump this 707 00:26:41,750 --> 00:26:43,819 intermediate netlist and see what what's 708 00:26:43,820 --> 00:26:44,820 going on. 709 00:26:48,160 --> 00:26:50,349 Yeah, as I've mentioned already, 710 00:26:50,350 --> 00:26:52,269 a formal verification of something that 711 00:26:52,270 --> 00:26:54,969 is very important for me, 712 00:26:54,970 --> 00:26:57,129 so I have to have a slightly 713 00:26:57,130 --> 00:26:59,199 different form of verification 714 00:26:59,200 --> 00:27:01,269 methods that can be used with users. 715 00:27:01,270 --> 00:27:03,669 There is a built in sova 716 00:27:03,670 --> 00:27:05,709 that can be used to answer simple 717 00:27:05,710 --> 00:27:08,199 questions, like is there any sequence 718 00:27:08,200 --> 00:27:10,359 of of of 719 00:27:10,360 --> 00:27:12,819 of any time steps 720 00:27:12,820 --> 00:27:14,979 where in the end the 721 00:27:14,980 --> 00:27:17,109 signal is high and the signal B is 722 00:27:17,110 --> 00:27:19,329 low and then it will try to find such 723 00:27:19,330 --> 00:27:20,559 a sequence. 724 00:27:20,560 --> 00:27:22,659 I actually used this quite a lot 725 00:27:22,660 --> 00:27:25,389 when when, when doing larger FPGA 726 00:27:25,390 --> 00:27:27,519 designs than you have to instrument 727 00:27:27,520 --> 00:27:29,409 and something like debugger. 728 00:27:29,410 --> 00:27:31,629 And you only can have so 729 00:27:31,630 --> 00:27:33,279 many signals that you look at and you 730 00:27:33,280 --> 00:27:35,469 want to back. So you end up with 731 00:27:35,470 --> 00:27:37,239 debug trace that say something like, oh, 732 00:27:37,240 --> 00:27:38,979 this signal is high and the signal is low 733 00:27:38,980 --> 00:27:40,779 in that time to look at this and you 734 00:27:40,780 --> 00:27:42,309 wonder how is this even possible? 735 00:27:42,310 --> 00:27:43,719 I don't see how this is possible. 736 00:27:43,720 --> 00:27:46,119 And usually you would need to 737 00:27:48,430 --> 00:27:50,169 recent the size, the entire design. 738 00:27:50,170 --> 00:27:52,359 I'd add more signals to to find 739 00:27:52,360 --> 00:27:54,069 out what happened to those signals so 740 00:27:54,070 --> 00:27:55,419 that they end up in this state. 741 00:27:55,420 --> 00:27:57,700 But with this technology, you can just 742 00:27:58,810 --> 00:28:00,819 take the design and say, I have observed 743 00:28:00,820 --> 00:28:02,979 that these two signals go to 744 00:28:02,980 --> 00:28:04,149 the states. 745 00:28:04,150 --> 00:28:05,319 What can cause this? 746 00:28:05,320 --> 00:28:06,969 And it will give you an answer. 747 00:28:06,970 --> 00:28:08,979 There is a large framework for 748 00:28:08,980 --> 00:28:10,479 equivalence checking, which is very 749 00:28:10,480 --> 00:28:12,459 important if you do things like writing a 750 00:28:12,460 --> 00:28:14,559 synthesis tool, because you would like to 751 00:28:14,560 --> 00:28:16,089 make sure that the output of your 752 00:28:16,090 --> 00:28:17,949 synthesis tool is formally equivalent to 753 00:28:17,950 --> 00:28:20,319 the input. So I added 754 00:28:20,320 --> 00:28:22,599 that you can do 755 00:28:22,600 --> 00:28:24,909 a property 756 00:28:24,910 --> 00:28:26,889 check and using meter circuits with the 757 00:28:26,890 --> 00:28:28,839 built in solvent with external solvers 758 00:28:28,840 --> 00:28:30,939 like in ABC, the soldiers that can 759 00:28:30,940 --> 00:28:31,749 be used for that. 760 00:28:31,750 --> 00:28:34,089 And of course there is this uses S&P, BMC 761 00:28:34,090 --> 00:28:35,619 flow that I mentioned before. 762 00:28:39,450 --> 00:28:41,549 So this is this is the 763 00:28:41,550 --> 00:28:43,859 floor with these three tools, 764 00:28:43,860 --> 00:28:46,049 we can we can implement everything 765 00:28:46,050 --> 00:28:48,329 we we 766 00:28:48,330 --> 00:28:50,729 we need we can we can build the signs. 767 00:28:50,730 --> 00:28:52,979 So so how do we do this? 768 00:28:52,980 --> 00:28:54,329 First, we need the development board 769 00:28:55,560 --> 00:28:57,119 and luckily there are a lot of 770 00:28:57,120 --> 00:28:59,319 development paths available. 771 00:28:59,320 --> 00:29:01,739 So let us know if you 772 00:29:01,740 --> 00:29:02,789 want. 773 00:29:02,790 --> 00:29:05,399 But there are also a lot of development 774 00:29:05,400 --> 00:29:08,039 parts and I'm not sure 775 00:29:08,040 --> 00:29:10,049 what's the percentage of them that have 776 00:29:10,050 --> 00:29:12,179 been inspired by the availability of 777 00:29:12,180 --> 00:29:14,400 this open source floor, 778 00:29:15,510 --> 00:29:17,879 which of those have been planned 779 00:29:17,880 --> 00:29:20,309 already before I published 780 00:29:20,310 --> 00:29:21,310 my book? 781 00:29:23,330 --> 00:29:25,429 But in the lower 782 00:29:25,430 --> 00:29:27,409 left corner, you see the Ichabod and the 783 00:29:27,410 --> 00:29:29,359 Ichabod's is actually a project I'm 784 00:29:29,360 --> 00:29:31,459 involved with, so I'm going to use 785 00:29:31,460 --> 00:29:32,759 that for for the demo. 786 00:29:34,190 --> 00:29:35,179 This is the Ichabod. 787 00:29:35,180 --> 00:29:37,579 It's a Raspberry Pi hat featuring 788 00:29:37,580 --> 00:29:40,279 the eight K FPGA, 789 00:29:40,280 --> 00:29:42,559 and it supports up to 20 pimlott 790 00:29:42,560 --> 00:29:45,859 parts. Then when you use 791 00:29:45,860 --> 00:29:47,419 extensions, balls that are connected to 792 00:29:47,420 --> 00:29:49,399 the flat flex connectors. 793 00:29:49,400 --> 00:29:51,499 So in total, you have almost 794 00:29:51,500 --> 00:29:54,439 200 eye opens on the respray with that. 795 00:29:54,440 --> 00:29:56,029 And I think this is something that can be 796 00:29:56,030 --> 00:29:57,439 useful even if you're not really 797 00:29:57,440 --> 00:29:59,779 interested in an open source FPGA 798 00:29:59,780 --> 00:30:00,780 toolchain. 799 00:30:01,490 --> 00:30:04,249 So there are a couple of applications. 800 00:30:04,250 --> 00:30:05,509 Of course, you can just make an 801 00:30:05,510 --> 00:30:08,209 intelligent Raspberry Pi expander 802 00:30:08,210 --> 00:30:10,279 that a little bit more than just 803 00:30:10,280 --> 00:30:12,709 exposing eyeballs. 804 00:30:12,710 --> 00:30:14,629 You can use the Raspberry Pi as a network 805 00:30:14,630 --> 00:30:17,269 Navot program and debugger, 806 00:30:17,270 --> 00:30:18,890 which is quite useful. 807 00:30:20,090 --> 00:30:22,249 And one bad idea that I 808 00:30:22,250 --> 00:30:24,559 like very much as you can actually 809 00:30:24,560 --> 00:30:26,839 create HDL called on the fly 810 00:30:26,840 --> 00:30:29,119 on the Raspberry Pi and synthesize 811 00:30:29,120 --> 00:30:31,339 it on the Raspberry Pi and program 812 00:30:31,340 --> 00:30:33,649 it into the FPGA without 813 00:30:33,650 --> 00:30:36,919 going to any external workstation 814 00:30:36,920 --> 00:30:38,989 that does the synthesis and bitstream 815 00:30:38,990 --> 00:30:40,220 generation step for you. 816 00:30:42,430 --> 00:30:45,009 So we've built a small demo, SLC, 817 00:30:45,010 --> 00:30:47,859 and I have two motivations 818 00:30:47,860 --> 00:30:49,809 for that. The first one is I would like 819 00:30:49,810 --> 00:30:51,879 to convince you that this 820 00:30:51,880 --> 00:30:53,559 toolchain can actually be used for 821 00:30:53,560 --> 00:30:55,719 non-trivial designs and not 822 00:30:55,720 --> 00:30:57,579 just small HelloWallet examples. 823 00:30:58,660 --> 00:31:00,699 And the second thing is this is a very 824 00:31:00,700 --> 00:31:02,319 small FPGA. 825 00:31:02,320 --> 00:31:04,449 So I would like to convince you that even 826 00:31:04,450 --> 00:31:06,609 with something that only has 8000 827 00:31:06,610 --> 00:31:08,859 lots, you can do 828 00:31:08,860 --> 00:31:10,749 interesting things. 829 00:31:10,750 --> 00:31:13,219 So my time, my demo 830 00:31:13,220 --> 00:31:15,489 of design here, my demo system 831 00:31:15,490 --> 00:31:17,559 on a chip uses only about 50 832 00:31:17,560 --> 00:31:19,389 percent of the logic resources on this 833 00:31:19,390 --> 00:31:20,799 FPGA. 834 00:31:20,800 --> 00:31:22,899 So it could also be very interesting 835 00:31:22,900 --> 00:31:24,579 as a basis for other projects because I 836 00:31:24,580 --> 00:31:26,319 still have half of the device for 837 00:31:26,320 --> 00:31:27,640 whatever you would like to add. 838 00:31:29,110 --> 00:31:31,179 And it includes a full feature, 839 00:31:31,180 --> 00:31:33,789 32 bit processor that's 840 00:31:33,790 --> 00:31:34,989 compatible with the risk. 841 00:31:34,990 --> 00:31:36,849 Five instructions set so you can use 842 00:31:36,850 --> 00:31:38,589 Jesusita, which can and stuff like that 843 00:31:38,590 --> 00:31:40,689 to to build 844 00:31:40,690 --> 00:31:41,690 programs for that. 845 00:31:42,910 --> 00:31:45,009 And in this demo, the Raspberry Pi 846 00:31:45,010 --> 00:31:47,469 is only used as a network enabled 847 00:31:47,470 --> 00:31:49,809 debugger and to access the console 848 00:31:49,810 --> 00:31:51,999 part of the system on a chip. 849 00:31:52,000 --> 00:31:53,140 It doesn't do anything else. 850 00:31:55,860 --> 00:31:58,499 So this is a simplified block diagram of 851 00:31:58,500 --> 00:31:59,779 of my my demo, 852 00:32:01,230 --> 00:32:03,359 you see all 853 00:32:03,360 --> 00:32:05,429 the things in pink 854 00:32:05,430 --> 00:32:08,069 as something that runs on the FPGA 855 00:32:08,070 --> 00:32:10,289 itself and you see the 856 00:32:10,290 --> 00:32:12,269 external components are like the rest. 857 00:32:12,270 --> 00:32:14,629 Rupi that's connected to this card 858 00:32:14,630 --> 00:32:16,859 that implements 859 00:32:16,860 --> 00:32:19,169 have two parallel communication 860 00:32:19,170 --> 00:32:20,759 link between the Raspberry Pi and the 861 00:32:20,760 --> 00:32:22,419 FPGA. 862 00:32:22,420 --> 00:32:24,869 And I could goes to various endpoints 863 00:32:24,870 --> 00:32:27,059 on the on the FPGA 864 00:32:27,060 --> 00:32:29,009 there is an on chip debugger. 865 00:32:29,010 --> 00:32:31,259 There is an endpoint that can be used 866 00:32:31,260 --> 00:32:34,079 to upload programs into the FPGA 867 00:32:34,080 --> 00:32:37,289 system. There is a text console, 868 00:32:37,290 --> 00:32:38,399 stuff like that. 869 00:32:38,400 --> 00:32:40,859 There is a two bit system 870 00:32:40,860 --> 00:32:42,809 that connects all the components in the 871 00:32:42,810 --> 00:32:43,810 system, 872 00:32:44,940 --> 00:32:46,589 like all those endpoints. 873 00:32:46,590 --> 00:32:49,439 Then the internal block memory, 874 00:32:49,440 --> 00:32:51,569 the Eslam controller that connects to the 875 00:32:51,570 --> 00:32:52,949 external externalism. 876 00:32:52,950 --> 00:32:55,109 We have a frame buffer here to 877 00:32:55,110 --> 00:32:57,059 talk to this lady matrix. 878 00:32:57,060 --> 00:32:59,249 We have a controller to access 879 00:32:59,250 --> 00:33:00,809 all the options. 880 00:33:00,810 --> 00:33:03,569 We have, of course, the processor itself 881 00:33:03,570 --> 00:33:05,879 and we have some some logic for clock 882 00:33:05,880 --> 00:33:06,880 management. 883 00:33:10,290 --> 00:33:12,059 So how do we synthesize something like 884 00:33:12,060 --> 00:33:14,309 this in this case, we're just 885 00:33:14,310 --> 00:33:16,949 using a makefile and 886 00:33:16,950 --> 00:33:19,079 here are the relevant make holes 887 00:33:19,080 --> 00:33:21,329 and you see the three steps that 888 00:33:21,330 --> 00:33:23,429 I had already on the first slide. 889 00:33:23,430 --> 00:33:25,499 I use Yosses to 890 00:33:25,500 --> 00:33:26,500 read the 891 00:33:27,570 --> 00:33:30,089 code, synthesize 892 00:33:30,090 --> 00:33:32,489 it and write it into a play file. 893 00:33:32,490 --> 00:33:34,889 Then they use Arachne to take that 894 00:33:34,890 --> 00:33:36,899 file and the placement constraint file 895 00:33:36,900 --> 00:33:39,659 and to turn it into a 896 00:33:39,660 --> 00:33:41,759 text file, a text representation of the 897 00:33:41,760 --> 00:33:42,989 FPGA bitstream. 898 00:33:42,990 --> 00:33:44,819 And then they use icepack to conduct this 899 00:33:44,820 --> 00:33:46,439 text representation into the actual 900 00:33:46,440 --> 00:33:48,509 binary file that can be programed 901 00:33:48,510 --> 00:33:49,909 into the FPGA. 902 00:33:51,810 --> 00:33:52,919 Additional are macros. 903 00:33:52,920 --> 00:33:54,780 When you look up the project 904 00:33:56,760 --> 00:33:58,919 to to build the actual firmware and stuff 905 00:33:58,920 --> 00:34:00,659 like that, using the risk five compiler 906 00:34:00,660 --> 00:34:02,729 toolchain and also additional 907 00:34:02,730 --> 00:34:03,730 macros for 908 00:34:04,920 --> 00:34:06,089 for programing. 909 00:34:06,090 --> 00:34:08,399 And there is a tool 910 00:34:08,400 --> 00:34:10,349 called I could block that runs on the 911 00:34:10,350 --> 00:34:12,329 Raspberry Pi and we can either run it 912 00:34:12,330 --> 00:34:14,468 locally in that case as 913 00:34:14,469 --> 00:34:16,948 each recipe is just as dachsie. 914 00:34:16,949 --> 00:34:19,169 So it's just using a shell 915 00:34:19,170 --> 00:34:21,149 to stop this program locally. 916 00:34:21,150 --> 00:34:22,948 But as I say, each recipe can also be 917 00:34:22,949 --> 00:34:25,589 just a call to SNH to 918 00:34:25,590 --> 00:34:28,109 use as a sage to connect to 919 00:34:28,110 --> 00:34:29,369 to the Raspberry Pi. 920 00:34:29,370 --> 00:34:31,529 And I could always read from an input 921 00:34:31,530 --> 00:34:33,928 and output so I can use just standing 922 00:34:33,929 --> 00:34:36,069 out for things like I'll use 923 00:34:36,070 --> 00:34:38,339 this binary and write it into 924 00:34:38,340 --> 00:34:40,408 the flesh in this 925 00:34:40,409 --> 00:34:41,409 case. 926 00:34:43,870 --> 00:34:45,939 Yeah, also mentioned the Onchi 927 00:34:45,940 --> 00:34:48,579 Baracoa, so 928 00:34:48,580 --> 00:34:50,678 you can just hook it up to to 929 00:34:50,679 --> 00:34:52,869 any nets you would like in your design 930 00:34:52,870 --> 00:34:54,129 and essentially get the logic. 931 00:34:54,130 --> 00:34:56,439 Analisa, you can write a few lines 932 00:34:56,440 --> 00:34:58,569 of code to find your 933 00:34:58,570 --> 00:35:00,999 trigger condition and to 934 00:35:01,000 --> 00:35:03,149 define what clock cycles you would like 935 00:35:03,150 --> 00:35:05,589 to keep in memory and 936 00:35:05,590 --> 00:35:07,089 what clock cycles you would like to 937 00:35:07,090 --> 00:35:08,090 ignore. 938 00:35:08,620 --> 00:35:10,929 And with the deep myth, the default 939 00:35:10,930 --> 00:35:12,709 environment, I have to make target called 940 00:35:12,710 --> 00:35:14,559 make debark that just connects to the 941 00:35:14,560 --> 00:35:17,139 widespread viruses and downloads 942 00:35:18,310 --> 00:35:20,289 velia change stamp file that can be 943 00:35:20,290 --> 00:35:22,329 displayed in the program like like TDK. 944 00:35:26,910 --> 00:35:29,039 Yeah, running applications on 945 00:35:29,040 --> 00:35:30,149 the system on a chip 946 00:35:31,980 --> 00:35:34,169 looks like this year 947 00:35:34,170 --> 00:35:36,149 when it first starts, you see the 948 00:35:36,150 --> 00:35:38,279 bootloader running and to put 949 00:35:38,280 --> 00:35:40,299 this place, this image of a floppy disk 950 00:35:40,300 --> 00:35:42,089 you see on the left, because that's where 951 00:35:42,090 --> 00:35:43,719 I think it should display. 952 00:35:45,030 --> 00:35:47,309 Then a couple of examples 953 00:35:47,310 --> 00:35:49,079 of programs that I wrote. 954 00:35:49,080 --> 00:35:51,269 And they just use this text console 955 00:35:51,270 --> 00:35:53,339 to talk to the bootloader and 956 00:35:53,340 --> 00:35:55,619 write a text representation 957 00:35:55,620 --> 00:35:58,469 of the hex of content 958 00:35:58,470 --> 00:35:59,699 to to the bootloader. 959 00:35:59,700 --> 00:36:01,289 And that writes it into the assignment 960 00:36:01,290 --> 00:36:02,290 and executed. 961 00:36:03,570 --> 00:36:06,239 Yeah. And I'd like to to to try that 962 00:36:06,240 --> 00:36:07,240 on. 963 00:36:08,760 --> 00:36:09,760 Mhere. 964 00:36:13,540 --> 00:36:14,540 It's. 965 00:36:17,000 --> 00:36:18,000 So. 966 00:36:23,550 --> 00:36:25,520 Yeah, something that, um. 967 00:36:26,560 --> 00:36:28,919 So, uh, oops. 968 00:36:31,850 --> 00:36:34,609 Um, let's just, 969 00:36:34,610 --> 00:36:37,129 uh, uh. 970 00:36:37,130 --> 00:36:38,130 These are put. 971 00:36:39,430 --> 00:36:40,430 So. 972 00:36:44,130 --> 00:36:45,449 That's taking too long. 973 00:36:55,940 --> 00:36:58,099 That's exactly what they wanted to avoid. 974 00:37:24,230 --> 00:37:25,230 Oh, 975 00:37:26,330 --> 00:37:27,330 OK. 976 00:37:29,750 --> 00:37:30,750 So. 977 00:37:31,930 --> 00:37:33,579 Luckily, I didn't suspect the software 978 00:37:33,580 --> 00:37:34,959 problem, so now we should see the 979 00:37:34,960 --> 00:37:36,929 bootloader, OK? 980 00:37:38,830 --> 00:37:41,350 And let me just. 981 00:37:43,240 --> 00:37:44,700 Make this a little bit smaller, so. 982 00:37:49,170 --> 00:37:51,239 And then let's, for example, 983 00:37:52,320 --> 00:37:53,320 do this show. 984 00:37:56,110 --> 00:37:57,110 So. 985 00:37:59,410 --> 00:38:01,209 So now we have hopefully 986 00:38:03,730 --> 00:38:05,360 started something. 987 00:38:21,080 --> 00:38:22,639 Unfortunately, can't go on because I 988 00:38:22,640 --> 00:38:23,640 don't have it here. 989 00:38:35,180 --> 00:38:36,639 Good. 990 00:38:36,640 --> 00:38:37,640 OK, 991 00:38:39,840 --> 00:38:41,909 so now we have this Christmas tree 992 00:38:41,910 --> 00:38:43,469 blinking. 993 00:38:43,470 --> 00:38:45,419 Let's go back to the FPGA director and 994 00:38:45,420 --> 00:38:47,269 say make the book. 995 00:38:47,270 --> 00:38:49,889 Um, so now we've downloaded 996 00:38:49,890 --> 00:38:52,409 256 sightings of tieback 997 00:38:52,410 --> 00:38:54,989 data from the Pilton debugger, 998 00:38:54,990 --> 00:38:57,899 and we can just display this, 999 00:38:57,900 --> 00:38:58,900 uh. 1000 00:39:00,180 --> 00:39:01,180 So. 1001 00:39:06,930 --> 00:39:07,930 So what's now? 1002 00:39:11,190 --> 00:39:12,190 Well, let's get. 1003 00:39:23,120 --> 00:39:25,399 OK, second 1004 00:39:25,400 --> 00:39:28,009 time it works. So now we have downloaded 1005 00:39:28,010 --> 00:39:29,869 something like that, and in this case I 1006 00:39:29,870 --> 00:39:31,969 have configured the built in debugger 1007 00:39:31,970 --> 00:39:34,159 to to monitor the memory posts 1008 00:39:34,160 --> 00:39:36,799 in the things we can see, the instruction 1009 00:39:36,800 --> 00:39:39,049 features and and every 1010 00:39:39,050 --> 00:39:41,449 now and then probably an instruction 1011 00:39:41,450 --> 00:39:42,450 fetch. 1012 00:39:45,680 --> 00:39:46,680 How do I. 1013 00:39:53,660 --> 00:39:56,149 OK. All instruction fetches 256 1014 00:39:56,150 --> 00:39:58,429 cyclists, not so much. 1015 00:39:58,430 --> 00:39:59,430 Uh. 1016 00:40:00,560 --> 00:40:02,749 OK, so we can see this is, 1017 00:40:02,750 --> 00:40:04,939 I think, really a nontrivial 1018 00:40:04,940 --> 00:40:07,399 system and 1019 00:40:07,400 --> 00:40:09,469 and shows that we have a toolchain 1020 00:40:09,470 --> 00:40:12,469 that can be used to do real world stuff 1021 00:40:12,470 --> 00:40:14,719 and not just very simple Healthwatch 1022 00:40:14,720 --> 00:40:15,800 like things. 1023 00:40:28,250 --> 00:40:30,319 OK, good. 1024 00:40:30,320 --> 00:40:31,320 Uh. 1025 00:40:33,100 --> 00:40:34,839 So how does it compare to the commercial 1026 00:40:34,840 --> 00:40:35,919 flow? 1027 00:40:35,920 --> 00:40:38,049 So there are two commercial flows 1028 00:40:38,050 --> 00:40:40,209 available from from Lettice. 1029 00:40:40,210 --> 00:40:42,279 They both use the letters 1030 00:40:42,280 --> 00:40:44,139 proprietary picante. 1031 00:40:44,140 --> 00:40:45,219 SBT beckoned. 1032 00:40:46,660 --> 00:40:49,119 But one of the two floors 1033 00:40:49,120 --> 00:40:51,219 is using simplifier pull as syntheses 1034 00:40:51,220 --> 00:40:53,619 front and the other one is using 1035 00:40:53,620 --> 00:40:55,819 Lettice LC as a system. 1036 00:40:55,820 --> 00:40:57,609 This is Fronton and we are comparing that 1037 00:40:57,610 --> 00:40:58,610 with Yosses and the 1038 00:41:01,540 --> 00:41:04,089 first couple of notes for this. 1039 00:41:04,090 --> 00:41:06,219 I'm using a version of the 1040 00:41:06,220 --> 00:41:08,289 latest tools that there's always almost 1041 00:41:08,290 --> 00:41:10,269 a year old. And the reason is that I have 1042 00:41:10,270 --> 00:41:12,579 wasted a day of my life 1043 00:41:12,580 --> 00:41:14,409 trying to activate the license for a 1044 00:41:14,410 --> 00:41:16,749 newer version and failed. 1045 00:41:18,260 --> 00:41:20,319 So I'm not sure how 1046 00:41:20,320 --> 00:41:23,259 it would compare with the uptodate 1047 00:41:23,260 --> 00:41:25,209 version of the lattice floor. 1048 00:41:25,210 --> 00:41:27,879 And the second thing is that 1049 00:41:27,880 --> 00:41:30,229 users might not be so good 1050 00:41:30,230 --> 00:41:32,949 when you look at logic optimization 1051 00:41:32,950 --> 00:41:35,349 and what you can do with the mappings. 1052 00:41:35,350 --> 00:41:37,599 But the audience is astonishingly 1053 00:41:37,600 --> 00:41:39,999 good with inferring memories 1054 00:41:40,000 --> 00:41:42,279 from behavioral code, in many 1055 00:41:42,280 --> 00:41:44,529 cases better than than 1056 00:41:44,530 --> 00:41:46,349 the many commercial tools. 1057 00:41:46,350 --> 00:41:48,819 And this is also the case here. 1058 00:41:48,820 --> 00:41:50,889 So when I used my design as 1059 00:41:50,890 --> 00:41:53,859 it was with the users, I 1060 00:41:53,860 --> 00:41:56,709 had something like 20 to placoderms, 1061 00:41:56,710 --> 00:41:59,049 but the other two toolchain 1062 00:41:59,050 --> 00:42:01,269 had also seven and eight blockhouse like 1063 00:42:01,270 --> 00:42:03,789 here but but like 80000 1064 00:42:03,790 --> 00:42:05,800 lookup tables because they are 1065 00:42:06,820 --> 00:42:07,929 back to it using 1066 00:42:09,030 --> 00:42:11,409 the Dealogic resources 1067 00:42:11,410 --> 00:42:13,569 to implement those memory resources 1068 00:42:13,570 --> 00:42:15,609 because they didn't know how to do things 1069 00:42:15,610 --> 00:42:17,589 like in from memory with byte. 1070 00:42:17,590 --> 00:42:20,589 And the rights are 1071 00:42:20,590 --> 00:42:22,869 in for memories with complex 1072 00:42:22,870 --> 00:42:25,119 and Abers and 1073 00:42:25,120 --> 00:42:27,249 the information architecture. 1074 00:42:27,250 --> 00:42:29,319 This is not a problem, but with the 1075 00:42:29,320 --> 00:42:30,519 ISO, the FPGA. 1076 00:42:30,520 --> 00:42:32,589 So you have to have an output register on 1077 00:42:32,590 --> 00:42:34,959 the block. So don't correctly infer 1078 00:42:34,960 --> 00:42:36,909 that with a neighbor you just can't use 1079 00:42:36,910 --> 00:42:38,439 the block business anymore. 1080 00:42:38,440 --> 00:42:39,440 So instead of 1081 00:42:40,660 --> 00:42:42,759 rewriting the entire design, 1082 00:42:42,760 --> 00:42:45,549 so it works on all three toolchain, 1083 00:42:45,550 --> 00:42:47,889 I made a stripped down version that's 1084 00:42:47,890 --> 00:42:50,079 not using the frame buffer because 1085 00:42:50,080 --> 00:42:51,080 blocking and resources 1086 00:42:52,390 --> 00:42:53,710 make some troubles. 1087 00:42:55,840 --> 00:42:58,269 And I also stripped down the internal 1088 00:42:58,270 --> 00:43:00,639 block to like for the arts or something 1089 00:43:00,640 --> 00:43:01,689 like that. 1090 00:43:01,690 --> 00:43:03,759 So it would be implemented 1091 00:43:03,760 --> 00:43:05,980 in logic. In both cases 1092 00:43:07,720 --> 00:43:09,789 you can see in terms 1093 00:43:09,790 --> 00:43:12,969 of packed logic cells, 1094 00:43:12,970 --> 00:43:15,009 the users are actually Penaflorida is a 1095 00:43:15,010 --> 00:43:17,079 little bit compared to the other 1096 00:43:17,080 --> 00:43:19,179 two floors, but it's not like the 1097 00:43:19,180 --> 00:43:20,180 world. 1098 00:43:20,860 --> 00:43:22,719 And the main reason for that is that 1099 00:43:22,720 --> 00:43:25,239 users at the moment too aggressive with 1100 00:43:25,240 --> 00:43:26,689 using the Kerry logic. 1101 00:43:26,690 --> 00:43:28,959 So you see we have almost 1102 00:43:28,960 --> 00:43:29,960 500 1103 00:43:31,690 --> 00:43:34,029 cells used and the other flows 1104 00:43:34,030 --> 00:43:36,609 only used three hundred and seventy two. 1105 00:43:36,610 --> 00:43:38,139 Because I'm too aggressive with 1106 00:43:38,140 --> 00:43:40,299 instantiating carry cells. 1107 00:43:40,300 --> 00:43:42,369 I often times a 1108 00:43:42,370 --> 00:43:44,769 fast a very, very small logic path 1109 00:43:44,770 --> 00:43:47,049 to one side of the carousel and another 1110 00:43:47,050 --> 00:43:48,549 logic path and the other side of the 1111 00:43:48,550 --> 00:43:50,649 carousel, and I end up with a 1112 00:43:50,650 --> 00:43:53,259 higher logic utilization. 1113 00:43:53,260 --> 00:43:55,449 So that's the main reason why why we 1114 00:43:55,450 --> 00:43:56,559 have this is different here. 1115 00:43:56,560 --> 00:43:58,239 But I think it's not the not the world. 1116 00:43:59,380 --> 00:44:01,029 But I find quite interesting is that 1117 00:44:01,030 --> 00:44:03,159 synthesis is more or less the same 1118 00:44:03,160 --> 00:44:05,259 time for all three floors like 1119 00:44:05,260 --> 00:44:06,759 this. Alesi is actually a little bit 1120 00:44:06,760 --> 00:44:08,989 faster in this case, but 1121 00:44:08,990 --> 00:44:11,349 the implementation time is 1122 00:44:11,350 --> 00:44:14,169 much, much smaller, 1123 00:44:14,170 --> 00:44:15,170 which 1124 00:44:16,240 --> 00:44:18,369 is much faster than the 1125 00:44:18,370 --> 00:44:20,019 battery pack and. 1126 00:44:22,090 --> 00:44:23,230 And a lot of this 1127 00:44:24,300 --> 00:44:25,300 thank you. 1128 00:44:28,660 --> 00:44:31,269 And a lot of this is because of 1129 00:44:31,270 --> 00:44:33,369 time when the commercial tours are 1130 00:44:33,370 --> 00:44:35,800 like loading of 1131 00:44:37,500 --> 00:44:39,189 that ship configuration and stuff like 1132 00:44:39,190 --> 00:44:41,349 that, because we prickish that 1133 00:44:41,350 --> 00:44:43,759 when you have virtually empty design 1134 00:44:43,760 --> 00:44:45,939 that just, I don't know, connect an input 1135 00:44:45,940 --> 00:44:47,769 directly to output, there's nothing else 1136 00:44:47,770 --> 00:44:49,929 you can create a bitstream in under a 1137 00:44:49,930 --> 00:44:51,699 second or maybe a second and a half. 1138 00:44:54,200 --> 00:44:56,779 So after a couple of links and 1139 00:44:56,780 --> 00:44:58,909 if you would like to scan this and get to 1140 00:44:58,910 --> 00:45:00,799 the to the link for this presentation, 1141 00:45:00,800 --> 00:45:01,849 for all the other links to 1142 00:45:03,740 --> 00:45:05,989 the slides are already online 1143 00:45:05,990 --> 00:45:06,949 on this location. 1144 00:45:06,950 --> 00:45:09,229 And I'll see if I can 1145 00:45:09,230 --> 00:45:11,449 also link them in the in the 1146 00:45:11,450 --> 00:45:12,450 proceedings online. 1147 00:45:13,550 --> 00:45:16,339 But but if not, just go to at 1148 00:45:16,340 --> 00:45:18,719 papers and then you will probably find 1149 00:45:18,720 --> 00:45:20,179 the link to to this. 1150 00:45:21,750 --> 00:45:24,689 Yeah, so the people 1151 00:45:24,690 --> 00:45:27,059 working on that on different 1152 00:45:27,060 --> 00:45:29,849 parts, the list is, of course, 1153 00:45:29,850 --> 00:45:32,119 incomplete and a lot of people 1154 00:45:32,120 --> 00:45:34,319 who just 1155 00:45:34,320 --> 00:45:36,449 contributed very small but 1156 00:45:36,450 --> 00:45:38,519 very important things like small 1157 00:45:38,520 --> 00:45:40,799 test cases to the expose box 1158 00:45:40,800 --> 00:45:42,629 is something that is always very, very 1159 00:45:42,630 --> 00:45:43,630 welcome. 1160 00:45:45,210 --> 00:45:46,889 And you also have an assembly here. 1161 00:45:46,890 --> 00:45:49,169 So please visit us 1162 00:45:49,170 --> 00:45:51,359 one on one. 1163 00:45:51,360 --> 00:45:53,519 So between the blinking area and 1164 00:45:53,520 --> 00:45:55,319 until meet the left, it's near by the 1165 00:45:55,320 --> 00:45:57,059 podcast. Podcasters are that the 3D 1166 00:45:57,060 --> 00:45:58,619 printers are. 1167 00:45:58,620 --> 00:46:00,689 We have we have more apps on 1168 00:46:00,690 --> 00:46:02,159 this thing that you can play with if you 1169 00:46:02,160 --> 00:46:03,160 want. 1170 00:46:03,750 --> 00:46:06,449 And we are also going to to do 1171 00:46:06,450 --> 00:46:08,459 workshops today, tomorrow and the day 1172 00:46:08,460 --> 00:46:10,829 after tomorrow at nineteen hundred. 1173 00:46:12,120 --> 00:46:14,219 So if you'd like to 1174 00:46:14,220 --> 00:46:16,319 have a hands on experience with this kind 1175 00:46:16,320 --> 00:46:18,569 of flowed and then please come to 1176 00:46:18,570 --> 00:46:20,639 our desk and register for those 1177 00:46:20,640 --> 00:46:22,769 workshops, if a lot of 1178 00:46:22,770 --> 00:46:25,019 people would like to see this 1179 00:46:25,020 --> 00:46:26,940 and then we will probably schedule 1180 00:46:27,990 --> 00:46:29,849 more workshops. 1181 00:46:29,850 --> 00:46:32,069 Yeah. And we also give a Ichabod's if 1182 00:46:32,070 --> 00:46:34,170 you have a cool project that you 1183 00:46:35,310 --> 00:46:37,589 think that would be nice 1184 00:46:37,590 --> 00:46:40,109 to demonstrate what I 1185 00:46:40,110 --> 00:46:42,179 can do, then we are all for it 1186 00:46:42,180 --> 00:46:44,519 and we'll give you a board. 1187 00:46:44,520 --> 00:46:45,520 Yeah. Thank you. 1188 00:46:50,290 --> 00:46:52,569 All right, so we have a good 1189 00:46:52,570 --> 00:46:54,669 10 minutes of questions and 1190 00:46:54,670 --> 00:46:56,289 answers, time left. 1191 00:46:56,290 --> 00:46:57,879 So if you have questions for Clifford, 1192 00:46:57,880 --> 00:47:00,819 please come to one of the microphones 1193 00:47:00,820 --> 00:47:02,079 in the SOL. 1194 00:47:02,080 --> 00:47:04,239 So everybody, even the people 1195 00:47:04,240 --> 00:47:05,739 watching the video or the screen can hear 1196 00:47:05,740 --> 00:47:06,969 you. 1197 00:47:06,970 --> 00:47:09,369 Um, and while 1198 00:47:09,370 --> 00:47:11,049 you are lining up at the microphones, we 1199 00:47:11,050 --> 00:47:12,489 are going to start with a question from 1200 00:47:12,490 --> 00:47:14,289 the signal, please. 1201 00:47:14,290 --> 00:47:16,479 Thank you, A.J., and wants to know he 1202 00:47:16,480 --> 00:47:17,949 has a question about partial 1203 00:47:17,950 --> 00:47:20,139 reconfiguration of space 1204 00:47:20,140 --> 00:47:21,789 with higher amount of gates. 1205 00:47:21,790 --> 00:47:24,099 Just the icy letters series have 1206 00:47:24,100 --> 00:47:26,379 internal configuration parts like 1207 00:47:26,380 --> 00:47:28,179 the Sitings FPGA do. 1208 00:47:30,230 --> 00:47:32,329 Short answer, no, there is 1209 00:47:32,330 --> 00:47:34,459 nothing that you can do for a partial 1210 00:47:34,460 --> 00:47:35,460 reconfiguration. 1211 00:47:36,740 --> 00:47:38,959 However, there is an 1212 00:47:38,960 --> 00:47:41,539 internal report card called WARMBLOOD 1213 00:47:41,540 --> 00:47:43,369 that can be used to reconfigure the 1214 00:47:43,370 --> 00:47:45,469 entire FPGA from 1215 00:47:45,470 --> 00:47:47,629 the FPGA. So it has to 1216 00:47:47,630 --> 00:47:49,519 select pins and one trigger pin. 1217 00:47:49,520 --> 00:47:51,979 And if you açaí the trigger pin, 1218 00:47:51,980 --> 00:47:53,929 then the to select Pennsville will 1219 00:47:53,930 --> 00:47:56,119 specify which of up to four 1220 00:47:56,120 --> 00:47:58,189 bitstream will be loaded in 1221 00:47:58,190 --> 00:48:00,229 the FPGA. So this is possible, but you 1222 00:48:00,230 --> 00:48:02,689 can partially reconfigure a device 1223 00:48:02,690 --> 00:48:03,690 while it's running. 1224 00:48:05,770 --> 00:48:07,839 OK, all right, then we're going to 1225 00:48:07,840 --> 00:48:08,859 go ahead with what 1226 00:48:10,330 --> 00:48:11,919 you said when you first started. 1227 00:48:11,920 --> 00:48:14,139 You got some emails about 1228 00:48:14,140 --> 00:48:15,129 the IP. 1229 00:48:15,130 --> 00:48:17,139 Have your relations with latish improved 1230 00:48:17,140 --> 00:48:18,249 since then? 1231 00:48:18,250 --> 00:48:20,709 Oh, it was not from from letters. 1232 00:48:20,710 --> 00:48:22,599 This was just just from er from a random 1233 00:48:22,600 --> 00:48:24,999 guy who, I don't know, saw 1234 00:48:25,000 --> 00:48:27,279 it on Hecate that that 1235 00:48:27,280 --> 00:48:29,769 I have done this and apparently 1236 00:48:29,770 --> 00:48:32,319 took it very personally and 1237 00:48:32,320 --> 00:48:34,779 thought I am after his IP 1238 00:48:34,780 --> 00:48:37,239 and so he sent me an email and 1239 00:48:37,240 --> 00:48:38,859 actually wrote that I should go to jail 1240 00:48:38,860 --> 00:48:39,909 for what I did. 1241 00:48:39,910 --> 00:48:41,800 It was quite an interesting experience. 1242 00:48:43,960 --> 00:48:45,849 OK, so we're going to mix in another 1243 00:48:45,850 --> 00:48:48,039 question from my Twitter. 1244 00:48:48,040 --> 00:48:49,899 Chris wants to know whether the error 1245 00:48:49,900 --> 00:48:52,299 messages are comprehensive. 1246 00:48:52,300 --> 00:48:54,399 For example, no resources left 1247 00:48:54,400 --> 00:48:56,110 or clock three is not feasible. 1248 00:48:59,010 --> 00:49:00,010 That's a good question. 1249 00:49:01,060 --> 00:49:04,269 I think for all stages 1250 00:49:04,270 --> 00:49:06,459 of of of the flaw, the error 1251 00:49:06,460 --> 00:49:07,640 messages could be better. 1252 00:49:11,840 --> 00:49:14,209 I know it in particular for users and 1253 00:49:14,210 --> 00:49:16,399 users, there is a lot of room 1254 00:49:16,400 --> 00:49:18,770 for improvement for things like 1255 00:49:19,790 --> 00:49:21,949 the input is not actually called. 1256 00:49:21,950 --> 00:49:24,169 Usually you just get syntax 1257 00:49:24,170 --> 00:49:26,179 in line so-and-so and then maybe it's 1258 00:49:26,180 --> 00:49:29,469 plus or minus five lines because 1259 00:49:29,470 --> 00:49:30,889 that that's how parcels are. 1260 00:49:32,510 --> 00:49:34,519 So so the error reporting is not very 1261 00:49:34,520 --> 00:49:36,889 good, but 1262 00:49:36,890 --> 00:49:39,049 usually you get an error 1263 00:49:39,050 --> 00:49:40,909 that that with at least some some 1264 00:49:40,910 --> 00:49:42,020 experience you can. 1265 00:49:43,030 --> 00:49:44,499 Trek back to the problem. 1266 00:49:45,760 --> 00:49:47,949 OK, perfect, Mike five, please. 1267 00:49:48,950 --> 00:49:50,709 Yeah, I would like to know a little more 1268 00:49:50,710 --> 00:49:52,249 about the support. 1269 00:49:52,250 --> 00:49:55,129 So you mentioned it shortly, but still 1270 00:49:55,130 --> 00:49:57,399 a schedule one which will 1271 00:49:57,400 --> 00:49:58,629 be supported. 1272 00:49:58,630 --> 00:50:00,759 No, right at 1273 00:50:00,760 --> 00:50:02,919 the moment there is someone 1274 00:50:02,920 --> 00:50:04,689 working on it, but I think there is no 1275 00:50:04,690 --> 00:50:05,690 cold yet. 1276 00:50:06,700 --> 00:50:09,309 There are two two ideas 1277 00:50:09,310 --> 00:50:11,379 how to support Vittel. 1278 00:50:11,380 --> 00:50:13,809 One one is they could 1279 00:50:13,810 --> 00:50:15,549 buy the new Verdell front end. 1280 00:50:15,550 --> 00:50:17,859 And the student was interested 1281 00:50:17,860 --> 00:50:19,999 in inviting, if you still want to, is 1282 00:50:20,000 --> 00:50:22,509 going to follow this approach 1283 00:50:22,510 --> 00:50:24,729 to the other possibility would be to 1284 00:50:24,730 --> 00:50:25,900 use some kind of 1285 00:50:26,980 --> 00:50:28,569 translator. 1286 00:50:28,570 --> 00:50:30,909 And there is an interesting 1287 00:50:30,910 --> 00:50:33,369 project that is part of Eco's, 1288 00:50:33,370 --> 00:50:35,739 which is the LP, 1289 00:50:35,740 --> 00:50:38,619 which is a preprocessor to convert 1290 00:50:38,620 --> 00:50:41,229 behavior Verdell into behavior 1291 00:50:41,230 --> 00:50:43,419 via a lock. And when you do that, you 1292 00:50:43,420 --> 00:50:45,069 actually can't do that. You need to add 1293 00:50:45,070 --> 00:50:47,499 more features to to the analog because 1294 00:50:47,500 --> 00:50:48,939 the simulation models are a little bit 1295 00:50:48,940 --> 00:50:50,769 different. But with synthesized area 1296 00:50:50,770 --> 00:50:52,779 code, it should actually be possible to 1297 00:50:52,780 --> 00:50:54,999 convert synthesizer Vittel 1298 00:50:55,000 --> 00:50:56,559 the syntax very long. 1299 00:50:56,560 --> 00:50:58,719 So maybe it would be possible to, like, 1300 00:50:58,720 --> 00:51:00,939 hack this tool to 1301 00:51:00,940 --> 00:51:02,259 to do that. 1302 00:51:02,260 --> 00:51:04,479 But but I am personally not working 1303 00:51:04,480 --> 00:51:06,789 on either of those because I'm 1304 00:51:06,790 --> 00:51:08,979 totally happy to be idealogue, 1305 00:51:08,980 --> 00:51:11,799 but I think that's my personal preference 1306 00:51:11,800 --> 00:51:12,859 for it. 1307 00:51:12,860 --> 00:51:15,279 Another question from the Antwerp's 1308 00:51:15,280 --> 00:51:17,379 2000 wants to know how powerful is 1309 00:51:17,380 --> 00:51:19,629 your Processo from the demo 1310 00:51:19,630 --> 00:51:21,969 in terms of registers and memory? 1311 00:51:21,970 --> 00:51:24,699 OK, so it's a it's a risk five 1312 00:51:24,700 --> 00:51:26,339 processor. 1313 00:51:26,340 --> 00:51:28,489 And if you've never heard of Risk five 1314 00:51:28,490 --> 00:51:30,669 before, it's a really, really cool 1315 00:51:30,670 --> 00:51:33,549 project that aims at creating 1316 00:51:33,550 --> 00:51:35,799 an open instruction set architecture that 1317 00:51:35,800 --> 00:51:37,959 is free of any 1318 00:51:37,960 --> 00:51:39,069 IP claims. 1319 00:51:39,070 --> 00:51:40,480 So you can implement 1320 00:51:41,770 --> 00:51:44,049 powerful processes with 1321 00:51:44,050 --> 00:51:46,299 with with instructions that architecture. 1322 00:51:46,300 --> 00:51:48,939 The process I have here is obviously 1323 00:51:48,940 --> 00:51:51,129 to it's it's a project of mine and 1324 00:51:51,130 --> 00:51:52,569 it's not very powerful because it's 1325 00:51:52,570 --> 00:51:54,009 optimized for size. 1326 00:51:54,010 --> 00:51:56,239 So on here, I think 1327 00:51:56,240 --> 00:51:58,569 it's less than than two thousand 1328 00:51:58,570 --> 00:52:00,959 lookup tables on Xilinx 1329 00:52:00,960 --> 00:52:03,129 seven series, which is my my 1330 00:52:03,130 --> 00:52:05,469 prime target architecture for this 1331 00:52:05,470 --> 00:52:07,509 chip in the smallest configuration, it's 1332 00:52:07,510 --> 00:52:09,759 smaller than 750 lookup 1333 00:52:09,760 --> 00:52:10,659 tables. 1334 00:52:10,660 --> 00:52:12,759 So it's a really, really small processor, 1335 00:52:12,760 --> 00:52:15,309 but it will take 1336 00:52:15,310 --> 00:52:17,469 four cycles approximately for each 1337 00:52:17,470 --> 00:52:19,599 instruction. It varies a little bit. 1338 00:52:19,600 --> 00:52:21,789 On the good side, you can clock it with 1339 00:52:21,790 --> 00:52:23,019 up to four megahertz. 1340 00:52:23,020 --> 00:52:25,199 So a lot of FPGA processors 1341 00:52:25,200 --> 00:52:26,739 want go to something like 60 megahertz, 1342 00:52:26,740 --> 00:52:29,659 then it evens out a little bit. 1343 00:52:29,660 --> 00:52:31,959 Risk five is a little bit instruction 1344 00:52:31,960 --> 00:52:34,319 set. And regarding the registers attached 1345 00:52:34,320 --> 00:52:36,639 to general-purpose registers, 1346 00:52:38,230 --> 00:52:40,449 thirty one because one is a zero register 1347 00:52:40,450 --> 00:52:42,449 always has zero and rights to it 1348 00:52:42,450 --> 00:52:43,450 diagnosed. 1349 00:52:43,970 --> 00:52:46,079 OK, all right, we still have time left, 1350 00:52:46,080 --> 00:52:47,989 so we are going to go over to Mike for 1351 00:52:47,990 --> 00:52:48,990 the next question. 1352 00:52:49,780 --> 00:52:52,059 And totally happy to see that 1353 00:52:52,060 --> 00:52:53,859 such a accessible, open 1354 00:52:55,150 --> 00:52:57,639 project for teaching 1355 00:52:57,640 --> 00:53:00,309 children in school or a classroom, 1356 00:53:00,310 --> 00:53:02,439 how the 1357 00:53:02,440 --> 00:53:04,759 process works from community 1358 00:53:04,760 --> 00:53:06,549 policy, specification of the process at 1359 00:53:06,550 --> 00:53:09,069 all to put pens and allows 1360 00:53:09,070 --> 00:53:11,629 for very cheap people 1361 00:53:11,630 --> 00:53:13,749 to really understand says to teach this. 1362 00:53:13,750 --> 00:53:15,069 This is awesome. 1363 00:53:15,070 --> 00:53:17,739 And and I'm wondering, 1364 00:53:17,740 --> 00:53:19,929 you mentioned that an interest of yours, 1365 00:53:19,930 --> 00:53:22,029 especially this verification, and 1366 00:53:22,030 --> 00:53:24,159 I wonder whether this can be shown on 1367 00:53:24,160 --> 00:53:26,229 the on the level 1368 00:53:26,230 --> 00:53:28,179 of the process that you mentioned is a 1369 00:53:28,180 --> 00:53:29,979 real science. You could say, oh, my all 1370 00:53:29,980 --> 00:53:32,139 put pen on the process, 1371 00:53:32,140 --> 00:53:33,639 went to a high and low. 1372 00:53:33,640 --> 00:53:36,069 And can you can you verify 1373 00:53:36,070 --> 00:53:37,090 on that size 1374 00:53:38,690 --> 00:53:41,409 does happen verification 1375 00:53:41,410 --> 00:53:44,469 tasks that I can run on my processor. 1376 00:53:44,470 --> 00:53:46,779 Generally, processors 1377 00:53:46,780 --> 00:53:48,909 are hard to formally verify because there 1378 00:53:48,910 --> 00:53:51,069 is this huge divergence of 1379 00:53:51,070 --> 00:53:52,749 control flow inherently having a 1380 00:53:52,750 --> 00:53:54,249 processor. 1381 00:53:54,250 --> 00:53:56,499 But there are things that I do 1382 00:53:56,500 --> 00:53:59,619 like, as I've I think 1383 00:53:59,620 --> 00:54:01,989 mentioned, the processors 1384 00:54:01,990 --> 00:54:03,759 configurable. There are features you can 1385 00:54:03,760 --> 00:54:05,889 turn on and turn off and they have 1386 00:54:05,890 --> 00:54:08,259 a form of proof that says 1387 00:54:08,260 --> 00:54:10,389 when I have two sets of of of 1388 00:54:10,390 --> 00:54:13,089 features and 1389 00:54:13,090 --> 00:54:15,489 the and I only look at 1390 00:54:15,490 --> 00:54:18,399 sequences of instructions that don't 1391 00:54:18,400 --> 00:54:20,859 let the less powerful 1392 00:54:20,860 --> 00:54:23,139 features that processor trap 1393 00:54:23,140 --> 00:54:25,719 then give more power for must always 1394 00:54:25,720 --> 00:54:27,459 have the same behavior. 1395 00:54:27,460 --> 00:54:28,989 And this is a kind of proof that I can 1396 00:54:28,990 --> 00:54:30,750 actually do with Mafiosos right now. 1397 00:54:32,290 --> 00:54:34,089 OK, before we go to the next question, 1398 00:54:34,090 --> 00:54:36,219 just a quick ask to the people in 1399 00:54:36,220 --> 00:54:38,049 the room coming in or leaving, please be 1400 00:54:38,050 --> 00:54:40,359 as quiet as possible so we can 1401 00:54:40,360 --> 00:54:41,769 finish the Q&A. 1402 00:54:41,770 --> 00:54:42,770 Mike five, please. 1403 00:54:43,800 --> 00:54:45,989 I want to say thank you very much for 1404 00:54:45,990 --> 00:54:48,089 doing this work to you and to 1405 00:54:48,090 --> 00:54:50,219 cottonseed, I think this is this 1406 00:54:50,220 --> 00:54:52,379 is the equivalent of the first version 1407 00:54:52,380 --> 00:54:54,509 of GCSE, but for 1408 00:54:54,510 --> 00:54:55,799 hardware. 1409 00:54:55,800 --> 00:54:57,569 So thank you very much for that. 1410 00:54:57,570 --> 00:54:58,570 Thank you. 1411 00:55:00,640 --> 00:55:02,890 All right, then we'll just stay with my. 1412 00:55:04,810 --> 00:55:07,119 Yeah, great project, but 1413 00:55:07,120 --> 00:55:09,309 what about timing, 1414 00:55:09,310 --> 00:55:11,499 validation and timing 1415 00:55:11,500 --> 00:55:12,840 during Disenrolled? 1416 00:55:14,020 --> 00:55:16,089 Yeah, right now none 1417 00:55:16,090 --> 00:55:18,279 of our processes are really timing 1418 00:55:18,280 --> 00:55:20,419 driven. There are some some very 1419 00:55:20,420 --> 00:55:22,359 weak timing driven optimizations and the 1420 00:55:22,360 --> 00:55:24,879 high level stuff just know it's better to 1421 00:55:24,880 --> 00:55:26,889 do this structure right instead of the 1422 00:55:26,890 --> 00:55:28,089 things like that. 1423 00:55:28,090 --> 00:55:30,159 Right now, the place and stuff is not 1424 00:55:30,160 --> 00:55:32,229 timing driven because we are still 1425 00:55:32,230 --> 00:55:34,659 working on uncrating timing 1426 00:55:34,660 --> 00:55:35,859 models. 1427 00:55:35,860 --> 00:55:37,719 But this is almost finished. 1428 00:55:39,400 --> 00:55:41,739 There are some 1429 00:55:41,740 --> 00:55:43,079 technical difficulties. 1430 00:55:43,080 --> 00:55:45,879 I think it's not not the right 1431 00:55:45,880 --> 00:55:48,219 moment now to the custom, but 1432 00:55:48,220 --> 00:55:50,679 I invite you to come to our assembly 1433 00:55:50,680 --> 00:55:52,330 and I would be happy to talk about it. 1434 00:55:54,130 --> 00:55:56,229 All right, then we're going to give the 1435 00:55:56,230 --> 00:55:58,359 people who are not able to be in 1436 00:55:58,360 --> 00:56:00,429 the room and the chance to 1437 00:56:00,430 --> 00:56:02,679 ask thank you, how does let us think 1438 00:56:02,680 --> 00:56:04,359 about your open source floor. 1439 00:56:04,360 --> 00:56:06,129 Are you in contact and what's coming 1440 00:56:06,130 --> 00:56:07,130 next? 1441 00:56:07,510 --> 00:56:09,619 Yeah, I don't know 1442 00:56:09,620 --> 00:56:11,309 if anyone from lettuce is here, please. 1443 00:56:13,480 --> 00:56:15,999 I would like to reach out to lettuce 1444 00:56:16,000 --> 00:56:18,249 as soon as I have a walking timing 1445 00:56:18,250 --> 00:56:20,559 flow, because that's the one thing 1446 00:56:20,560 --> 00:56:22,959 that's still missing right now. 1447 00:56:22,960 --> 00:56:24,819 And in my experience with all these 1448 00:56:24,820 --> 00:56:26,469 projects, with yours and all the other 1449 00:56:26,470 --> 00:56:29,169 stuff, whenever I approach 1450 00:56:29,170 --> 00:56:31,329 some kind of commercial entity, they 1451 00:56:31,330 --> 00:56:33,429 just don't believe that I can do 1452 00:56:33,430 --> 00:56:35,619 what I say I will do. 1453 00:56:35,620 --> 00:56:37,899 So I would like to have complete floor 1454 00:56:37,900 --> 00:56:40,059 that is really production right there and 1455 00:56:40,060 --> 00:56:42,339 then say, here it is. 1456 00:56:42,340 --> 00:56:43,959 Maybe you would like to work with me 1457 00:56:43,960 --> 00:56:46,209 together to improve on 1458 00:56:46,210 --> 00:56:47,210 it. 1459 00:56:47,560 --> 00:56:49,629 OK, two more minutes, so to 1460 00:56:49,630 --> 00:56:51,429 get as many questions in as possible, 1461 00:56:51,430 --> 00:56:53,529 please make it short and precise, Mike, 1462 00:56:53,530 --> 00:56:54,530 to please. 1463 00:56:56,260 --> 00:56:57,549 Do you think it would be feasible to 1464 00:56:57,550 --> 00:56:59,649 design and fabricate a 1465 00:56:59,650 --> 00:57:01,929 independent FPGA that would be compatible 1466 00:57:01,930 --> 00:57:04,449 with this file format using 1467 00:57:04,450 --> 00:57:06,010 open micro libraries? 1468 00:57:07,270 --> 00:57:09,729 I think it would be possible, 1469 00:57:09,730 --> 00:57:12,069 but it 1470 00:57:12,070 --> 00:57:14,319 would be not 1471 00:57:14,320 --> 00:57:17,079 really much harder to just make your own 1472 00:57:17,080 --> 00:57:19,929 FPGA design and use these tools 1473 00:57:19,930 --> 00:57:22,089 and create a database similar to 1474 00:57:22,090 --> 00:57:24,189 the database we are using here 1475 00:57:24,190 --> 00:57:25,449 and things like that. 1476 00:57:25,450 --> 00:57:26,619 And there are actually 1477 00:57:27,850 --> 00:57:29,979 projects going on right now. 1478 00:57:29,980 --> 00:57:31,659 We're thinking about doing stuff like 1479 00:57:31,660 --> 00:57:33,879 that, creating our own FPGA. 1480 00:57:33,880 --> 00:57:36,129 So for me, this 1481 00:57:36,130 --> 00:57:38,049 is of course interesting to really have 1482 00:57:38,050 --> 00:57:40,269 support for an FPGA, but it 1483 00:57:40,270 --> 00:57:43,809 was also important. 1484 00:57:43,810 --> 00:57:45,879 So I can just show that my thoughts 1485 00:57:45,880 --> 00:57:47,800 and can can deliver. 1486 00:57:49,000 --> 00:57:51,489 Over 10 years ago, I tried to approach 1487 00:57:51,490 --> 00:57:53,589 some companies and 1488 00:57:53,590 --> 00:57:55,629 convince them to build an open source 1489 00:57:55,630 --> 00:57:58,209 FPGA and essentially all that openness. 1490 00:57:58,210 --> 00:57:59,859 It's completely impossible because we 1491 00:57:59,860 --> 00:58:01,839 will never have to open source toolchain 1492 00:58:01,840 --> 00:58:04,059 now we have to open source toolchain so 1493 00:58:04,060 --> 00:58:06,219 I can go back to that and see if 1494 00:58:06,220 --> 00:58:08,319 we can get an open source FPGA 1495 00:58:08,320 --> 00:58:10,209 fabricated, OK. 1496 00:58:10,210 --> 00:58:12,309 And I think our last question is coming 1497 00:58:12,310 --> 00:58:14,109 from someone watching the stream. 1498 00:58:14,110 --> 00:58:16,119 Again, I actually have two. 1499 00:58:16,120 --> 00:58:18,369 One is can you run over on OS? 1500 00:58:18,370 --> 00:58:20,319 And the second one is what you think it 1501 00:58:20,320 --> 00:58:22,029 would be possible to leverage your work 1502 00:58:22,030 --> 00:58:24,339 on the FPGA device to reverse engineer 1503 00:58:24,340 --> 00:58:25,340 other devices? 1504 00:58:26,350 --> 00:58:27,999 How would approach look like? 1505 00:58:30,910 --> 00:58:33,779 I looked into the data on 1506 00:58:33,780 --> 00:58:36,069 each day and decided I can process 1507 00:58:36,070 --> 00:58:38,229 them with the dialog in 1508 00:58:38,230 --> 00:58:40,539 the default configuration, they 1509 00:58:40,540 --> 00:58:43,329 would like to use multiplier 1510 00:58:43,330 --> 00:58:45,669 primitivist of exiling specific. 1511 00:58:45,670 --> 00:58:47,859 So that would be something that 1512 00:58:47,860 --> 00:58:49,599 would lead some changes. 1513 00:58:49,600 --> 00:58:51,669 But but it should be possible. 1514 00:58:51,670 --> 00:58:53,799 And, A.J., I think we should also 1515 00:58:53,800 --> 00:58:56,079 be large enough for 1516 00:58:56,080 --> 00:58:57,759 the one thing. 1517 00:58:57,760 --> 00:58:59,079 I didn't really get the second part of 1518 00:58:59,080 --> 00:59:00,099 the question, but I think we're out of 1519 00:59:00,100 --> 00:59:01,100 time anyway. 1520 00:59:01,750 --> 00:59:03,879 But you had your contact details. 1521 00:59:03,880 --> 00:59:05,979 So people here who still have 1522 00:59:05,980 --> 00:59:07,269 questions and also people from the 1523 00:59:07,270 --> 00:59:08,949 Internet can probably get in contact with 1524 00:59:08,950 --> 00:59:11,019 you. So thanks for the 1525 00:59:11,020 --> 00:59:13,029 talk. Thanks for the people asking. 1526 00:59:13,030 --> 00:59:14,030 Thanks for having me.